SLUS593J December   2003  – June 2022 TPS40054 , TPS40055 , TPS40057

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Setting the Switching Frequency (Programming the Clock Oscillator)
      2. 7.3.2 Programming The Ramp Generator Circuit
      3. 7.3.3 UVLO Operation
      4. 7.3.4 BP5 and BP10 Internal Voltage Regulators
      5. 7.3.5 Programming Soft Start
      6. 7.3.6 Programming Current Limit
      7. 7.3.7 Synchronizing to an External Supply
      8. 7.3.8 Loop Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting the Inductor Value
      2. 8.1.2 Calculating the Output Capacitance
      3. 8.1.3 Calculating the Boost and BP10 Bypass Capacitor
      4. 8.1.4 DV-DT Induced Turn-On
      5. 8.1.5 High-Side MOSFET Power Dissipation
      6. 8.1.6 Synchronous Rectifier MOSFET Power Dissipation
      7. 8.1.7 TPS4005x Power Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Calculate Maximum and Minimum Duty Cycles
        2. 8.2.2.2  Select Switching Frequency
        3. 8.2.2.3  Select ΔI
        4. 8.2.2.4  Calculate the High-Side MOSFET Power Losses
        5. 8.2.2.5  Calculate Synchronous Rectifier Losses
        6. 8.2.2.6  Calculate the Inductor Value
        7. 8.2.2.7  Set the Switching Frequency
        8. 8.2.2.8  Program the Ramp Generator Circuit
        9. 8.2.2.9  Calculate the Output Capacitance (CO)
        10. 8.2.2.10 Calculate the Soft-Start Capacitor (CSS/SD)
        11. 8.2.2.11 Calculate the Current Limit Resistor (RILIM)
        12. 8.2.2.12 Calculate Loop Compensation Values
        13. 8.2.2.13 Calculate the Boost and BP10V Bypass Capacitance
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 MOSFET Packaging
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Electrical Characteristics

TA = –40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY
VINInput voltage range, VIN840V
OPERATING CURRENT
IDDQuiescent currentOutput drivers not switching, VFB ≥ 0.75 V1.53mA
BP5
VBP5Output voltageIO ≤ 1 mA4.755.2V
OSCILLATOR/RAMP GENERATOR
fOSCAccuracy8 V ≤ VIN ≤ 40 V470520570kHz
VRAMPPWM ramp voltage(1)VPEAK – VVAL2V
VIHHigh-level input voltage, SYNC2
VILLow-level input voltage, SYNC0.8V
ISYNCInput current, SYNC510µA
Pulse width, SYNC50ns
VRTRT voltage2.382.52.58V
DMAXMaximum duty cycleVFB = 0 V, fSW ≤ 500 kHz85%94%
VFB = 0 V, 500 kHz ≤ fSW ≤ 1 MHz(1)80%
Minimum duty cycleVFB ≥ 0.75 V0%
VKFFFeed-forward voltage3.353.483.65V
IKFFFeedforward current operating range(1) (2)201100µA
SOFT START
ISS/SDSoft-start source current1.652.352.95µA
VSS/SDSoft-start clamp voltage3.7V
tDSCHDischarge timeCSS/SD = 220 pF1.62.22.8µs
tSS/SDSoft-start timeCSS/SD = 220 pF, 0 V ≤ VSS/SD ≤ 1.6 V115150215
BP10
VBP10Output voltageIO ≤ 1 mA99.610.3V
ERROR AMPLIFIER
VFBFeedback input voltage8 V ≤ VIN ≤ 40 V, TA = 25°C0.6980.70.704V
8 V ≤ VIN ≤ 40 V, 0°C ≤ TA ≤ 85°C0.6930.70.707
8 V ≤ VIN ≤ 40 V, -40°C≤ TA ≤ 85°C0.6930.70.715
GBWGain bandwidth(1)35MHz
AVOLOpen loop gain6080dB
IOHHigh-level output source current24mA
IOLLow-level output sink current24
VOHHigh-level output voltageISOURCE = 500 µA3.23.5V
VOLLow-level output voltageISINK = 500 µA0.20.35
IBIASInput bias currentVFB = 0.7 V100200nA
CURRENT LIMIT
ISINKCurrent limit sink current8.51011.5µA
Propagation delay to outputVILIM = 23.7 V, VSW = (VILIM – 0.5 V)300ns
VILIM = 23.7 V, VSW = (VILIM – 2 V)200
tONSwitch leading-edge blanking pulse time(1)100
tOFFOff time during a fault (soft-start cycle time)7cycles
VOSOffset voltage SW versus ILIMTA = 25°C–90–70–50mV
VILIM = 23.6 V, 0°C ≤ TA ≤ 85°C–120–38
VILIM = 23.6 V, -40°C ≤ TA ≤ 85°C–120–20
OUTPUT DRIVER
tLRISELow-side driver rise timeCLOAD = 2200 pF4896ns
tLFALLLow-side driver fall time2448
tHRISEHigh-side driver rise timeCLOAD = 2200 pF (HDRV – SW)4896
tHFALLHigh-side driver fall time3672
VOHHigh-level output voltage, HDRVIHDRV = –0.1 A (HDRV – SW)VBOOST
–1.5 V		VBOOST
–1 V		V
VOLLow-level ouput voltage, HDRVIHDRV = 0.1 A (HDRV – SW)0.75
VOHHigh-level ouput voltage, LDRVILDRV = –0.1 AVBP10
–1.4 V		VBP10
– 1 V
VOLLow-level output voltage, LDRVILDRV = 0.1 A0.5
Minimum controllable pulse width100150ns
SS/SD SHUTDOWN
VSDShutdown threshold voltageOutputs off90125160mV
VENDevice active threshold voltage190210245
BOOST REGULATOR
VBOOSTOutput voltageVIN= 24 V31.232.233.5V
RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 ONLY)
VSWSwitch voltageLDRV output OFF–10–50mV
SW NODE
ILEAKLeakage current(1) (out of pin)25µA
THERMAL SHUTDOWN
TSDShutdown temperature(1)165°C
Hysteresis(1)20
UVLO
VUVLOKFF programmable threshold voltageRKFF = 28.7 kΩ6.957.57.95V
VDDUVLO, fixed7.27.57.9
VDDUVLO, hysteresis0.46
(1) Specified by design. Not production tested.
(2) IKFF increases with SYNC frequency, maximum duty cycle decreases with IKFF.