SLUS593J December   2003  – June 2022 TPS40054 , TPS40055 , TPS40057

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Setting the Switching Frequency (Programming the Clock Oscillator)
      2. 7.3.2 Programming The Ramp Generator Circuit
      3. 7.3.3 UVLO Operation
      4. 7.3.4 BP5 and BP10 Internal Voltage Regulators
      5. 7.3.5 Programming Soft Start
      6. 7.3.6 Programming Current Limit
      7. 7.3.7 Synchronizing to an External Supply
      8. 7.3.8 Loop Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting the Inductor Value
      2. 8.1.2 Calculating the Output Capacitance
      3. 8.1.3 Calculating the Boost and BP10 Bypass Capacitor
      4. 8.1.4 DV-DT Induced Turn-On
      5. 8.1.5 High-Side MOSFET Power Dissipation
      6. 8.1.6 Synchronous Rectifier MOSFET Power Dissipation
      7. 8.1.7 TPS4005x Power Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Calculate Maximum and Minimum Duty Cycles
        2. 8.2.2.2  Select Switching Frequency
        3. 8.2.2.3  Select ΔI
        4. 8.2.2.4  Calculate the High-Side MOSFET Power Losses
        5. 8.2.2.5  Calculate Synchronous Rectifier Losses
        6. 8.2.2.6  Calculate the Inductor Value
        7. 8.2.2.7  Set the Switching Frequency
        8. 8.2.2.8  Program the Ramp Generator Circuit
        9. 8.2.2.9  Calculate the Output Capacitance (CO)
        10. 8.2.2.10 Calculate the Soft-Start Capacitor (CSS/SD)
        11. 8.2.2.11 Calculate the Current Limit Resistor (RILIM)
        12. 8.2.2.12 Calculate Loop Compensation Values
        13. 8.2.2.13 Calculate the Boost and BP10V Bypass Capacitance
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 MOSFET Packaging
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Programming The Ramp Generator Circuit

The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feedforward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations because the PWM does not have to wait for loop delays before changing the duty cycle (see Figure 7-1).

GUID-955C8278-D82E-4738-9BD5-8D1D71BBEF30-low.gifFigure 7-1 Voltage Feedforward Effect on PWM Duty Cycle

The PWM ramp must be faster than the controller clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed through a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the minimum input voltage, VIN(min), through the following:

Equation 2. GUID-942FBD91-DB5B-49D7-932C-43957A6A50F9-low.gif

where

  • VIN(min) is the ensured minimum start-up voltage (the actual start-up voltage is nominally about 10% lower at 25°C). VIN(min) must be programmed equal to or greater than 8 V to ensure start-up and shutdown through the programmed UVLO through the KFF pin.
  • RT is the timing resistance in kΩ.
  • VKFF is the voltage at the KFF pin (typical value is 3.48 V).

The curve showing the RKFF required for a given switching frequency, fSW, and VUVLO is shown in Figure 6-2.

For low-input voltage and high duty-cycle applications, the voltage feedforward can limit the duty cycle prematurely, but does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltage. For more information on large duty cycle operation, refer to the Effect of Programmable UVLO on Maximum Duty Cycle application note.