SLUS659G FEBRUARY   2006  – November 2014 TPS40200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 MOSFET Gate Drive
      2. 7.3.2 Undervoltage Lockout Protection
      3. 7.3.3 Selecting the Operating Frequency
      4. 7.3.4 Synchronizing the Oscillator
      5. 7.3.5 Current Limit Resistor Selection
      6. 7.3.6 Calculating the Soft-Start Time
      7. 7.3.7 Voltage Setting and Modulator Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With SS Pin
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Buck Regulator, 8 V to 12 V Input, 3.3 V to 5.0 V at 2.5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 FET Selection Criteria
          2. 8.2.1.2.2 Rectifier Selection Criteria
          3. 8.2.1.2.3 Inductor Selection Criteria
          4. 8.2.1.2.4 Output Capacitance
          5. 8.2.1.2.5 Switching Frequency
          6. 8.2.1.2.6 Calculating the Overcurrent Threshold Level
          7. 8.2.1.2.7 Soft-Start Capacitor
          8. 8.2.1.2.8 Frequency Compensation
            1. 8.2.1.2.8.1 Step 1
            2. 8.2.1.2.8.2 Step 2
            3. 8.2.1.2.8.3 Step 3
            4. 8.2.1.2.8.4 Step 4
            5. 8.2.1.2.8.5 Step 5
          9. 8.2.1.2.9 Printed Circuit Board Plots
        3. 8.2.1.3 Application Curves
      2. 8.2.2 18 V - 50 V Input, 16 V at 1-A Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedures
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Wide Input Voltage Led Constant Current Driver
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedures
        3. 8.2.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Products
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • Keep the AC current loops as short as possible. For the maximum effectiveness from C3, place it near the VDD pin of the controller and design the input AC loop consisting of C1-RSENSE-Q1-D1 to be as short as possible. Excessive high frequency noise on VDD during switching degrades overall regulation as the load increases.
  • Keep the output loop A (D1-L1-C2) as small as possible. A larger loop can degrade the application output noise performance.
  • Traces carrying large AC currents should NOT be connected through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield. Split the ground plane as necessary to keep noise away from the TPS40200 and noise sensitive areas such as feedback resistors R6, and R10.
  • Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated emissions.
  • For good output voltage regulation, Kelvin connections should be brought from the load to R6 and R10.
  • The trace from the R6-R10 junction to the TPS40200 should be short and kept away from any noise source (such as the SW node).
  • The gate drive trace should be as close as possible to the power FET gate.

10.2 Layout Example

v07045_lus659.gifFigure 49. PC Board Layout Recommendations