7.3.1 Voltage Reference

The 600-mV band gap cell is internally connected to the non-inverting input of the error amplifier. The reference voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The 0.5% tolerance on the reference voltage allows the user to design a very accurate power supply.

7.3.2 Output Voltage Setting

The output voltages of the TPS40322 are set by using external feedback resistor dividers as shown in Figure 15. The regulated output voltage (V_OUT) is determined by Equation 1.

Figure 15. Setting the Output Voltage

Equation 1.

7.3.3 Input Voltage Feedforward

The TPS40322 uses input voltage feedforward to maintain a constant power stage gain as the input voltage varies and provides very good response to input voltage transient disturbances. The simple constant power stage gain of the controller greatly simplifies feedback loop design because the loop characteristics remain constant as the input voltage changes, unlike a typical buck converter without voltage feedforward. For modeling purposes, the gain from the COMP pin to the average voltage at the input of the L-C filter is typically 8.5 V/V.

7.3.4 Current Sensing

The TPS40322 uses a differential current sense design to sense the output current. The sense element can be the series resistance of the power stage filter inductor or a separate current sense resistor. When using the inductor series resistance as shown in Figure 16, an R-C filter must be used to remove the large AC component voltage across the inductor so that only the component of the voltage that remains is across the resistance of the inductor (see Figure 16).

The values of R1 and C1 for an ideal design can be calculated using Equation 2. The time constant of the R-C filter must equal the time constant of the inductor itself. If the time constants are equal, the voltage across C1 equals the current in the inductor multiplied by the inductor resistance. The inductor ripple current is reflected in the voltage across C1. Typically a capacitor with a value of 0.1-µF is recommended for C1.

Refer to the Layout section for proper placement of the sensing elements.

Figure 16. Inductor DCR Current Sensing

Equation 2.

7.3.5 Overcurrent Protection

The TPS40322 has dedicated ILIM pins for each channel for use when operating in dual-output mode. When operating in two-phase mode, both channels share the same overcurrent level set by ILIM1. The overcurrent level is set with a resistor connected from the ILIMx pin to analog ground. The sensed current signal is amplified by the CS amplifier with a gain of 15, and then compared with the established overcurrent level to determine if there is an OC fault. This design is shown in Figure 17.

Figure 17. Overcurrent Protection

Equation 3 is the current limit resistance (R_LIM) calculation for desired overcurrent limit.

Equation 3.

where

• I_OC is the desired DC over current limit level
• I_RIPPLE is the inductor peak-peak ripple current
• DCR is the inductor DC resistance
• A_CS is the current sensing amplifier gain (typically 15)
• I_ILIM is the internal source current out of ILIMx pin (typically 10 µA)

The TPS40322 implements cycle-by-cycle current limit when the inductor peak current has exceeded the set limit. When the controller counts three consecutive clock cycles of an overcurrent condition, the high-side and low-side MOSFETs are turned off and the controller enters a hiccup mode. After six soft-start cycles, normal switching is attempted. If the overcurrent has cleared, normal operation resumes, otherwise the sequence repeats.

7.3.6 Two-Phase Mode, Remote Sense Amplifier, and Current Sharing Loop

The TPS40322 can be configured to operate in single-output, two-phase mode for high-current applications. With proper selection of the external MOSFETs, this device can support up to 50-A of load current in a two-phase configuration. As shown in Figure 18, to configure the TPS40322 for two-phase mode, FB2 is tied to BP6. In this mode, COMP1 must be connected to COMP2 to ensure current sharing between the two phases. For high-current applications, the remote sense amplifier is used to compensate for the parasitic offset to provide an accurate output voltage. The EN2/SS2 and ILIM2 pins are designed for multiple functions. They are used as VSNS and GSNS for remote sensing in two-phase mode. DIFFO, which is the output of the remote sensing amplifier, is connected to the resistor divider of the feedback network.

Note that BP6 powers the remote sense amplifier. The DIFFO voltage must be 0.2-V lower than the BP6 voltage under all conditions. If BP6 is lower than DIFFO voltage, the converter loses regulation. To ensure no regulation loss, use a remote sense amplifier when the application output voltage is lower than 2.2 V. For an application in which the output voltage is higher than 2.2 V, the remote sense amplifier can be bypassed and the voltage output can be connected to the feedback resistor divider directly.

Figure 18. Two-Phase Mode Voltage Loop Configuration

When the device operates in two-phase mode, a current sharing loop as shown in Figure 19 is designed to maintain the current balance between phases. Both phases share the same comparator voltage (COMP1). The sensed current from each phase is compared first in a current share block, then each signal is summed with COMP. The resulted error voltage is compared with the voltage ramp to generate the PWM pulse for each channel.

Figure 19. Two-Phase Mode Current Share Loop

7.3.7 Start-Up and Shutdown

7.3.7.1 Start-Up Sequence

When the ENx/SSx pin is pulled below 0.3 V, the respective channel is disabled. When ENx/SSx is released, the controller starts automatically and an internal 40-µA current source begins to charge the external soft-start capacitor. When the voltage across the soft-start capacitor is over 0.7 V, the internal BP regulator is enabled. The ENx/SSx voltage is clamped to 1.3 V while waiting for signals indicating that BP6, VDD, and the oscillator clock are good. After all the signals are confirmed, ENx/SSx is discharged to 0.4 V with a 140-µA current source, and then charged again with the internal 10-µA current source. The operation is described by the waveform shown in Figure 20. V_{SS_INT} is an internal signal level shifted from ENx/SSx and then connected to the non-inverting terminal of the error amplifier.

Figure 20. EN/SS Start-Up Waveform

The soft-start time is determined by the internal charge current and the external capacitance. The actual output ramp-up time is the time for the internal current source to charge the capacitor through a 600-mV range. There is some initial lag time due to the offset (800 mV typical) from the actual ENx/SSx pin voltage to V_{SS_INT}. The soft-start sequence takes place in a closed loop fashion, meaning that the error amplifier controls the output voltage constantly during the soft-start period and the feedback loop is never open (as occurs in duty cycle limit soft-start designs). The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and the other connected to the offset V_{SS_INT}. The error amplifier controls the FB pin to the lower of these two voltages. As the voltage on the ENx/SSx pin ramps up past approximately 1.4 V (800-mV offset voltage plus the 600-mV reference voltage), the 600-mV reference voltage becomes the dominant input and the converter has reached its final regulation voltage.

Equation 4 is the calculation for soft-start capacitance.

Equation 4.

where

• C_SS is the soft-start capacitance connected to ENx/SSx pin
• t_SS is the desired soft-start time
• I_SS is the internal soft-start current (typically 10 µA)

7.3.8 Switching Frequency and Master or Slave Synchronization

The switching frequency is set by the value of the resistor connected from the RT pin to AGND. The RT resistor value is calculated in Equation 5.

Equation 5.

where

• R_RT is the the resistor from RT pin to AGND, in Ω
• f_SW is the desired switching frequency, in Hz

The TPS40322 device can also synchronize to an external clock that is ±20% of the master clock frequency which is two times the free running frequency. Each TPS40322 can be set by the PHSET pin as either master or slave. The master produces a 50% duty cycle clock to the slave. The slave synchronizes to the external clock with 50% duty cycle and selects the phase shift angle as shown in Table 1.

Figure 21 shows an example of synchronizing two TPS40322 devices to generate an evenly distributed shift to reduce input ripple.

Figure 21. Synchronizing Two TPS40322 Devices

7.3.9 Overvoltage and Undervoltage Fault Protection

The TPS40322 has output overvoltage protection and undervoltage protection capability. The comparators that regulate the overvoltage and undervoltage conditions use the FBx pin as the output sensing point so the filtering effect of the compensation network connected from COMPx to FBx has an effect on the speed of detection. As the output voltage rises or falls below the nominal value, the error amplifier attempts to force FBx to match its reference voltage. When the error amplifier is no longer able to do this, the FB pin begins to drift and trip the overvoltage threshold (V_OVP) or the undervoltage threshold (V_UVP) as described in the Electrical Characteristics table.

When an undervoltage fault is detected, the TPS40322 enters hiccup mode and resumes normal operation when the fault is cleared.

When an overvoltage fault is detected, the TPS40322 turns off the high-side MOSFET and latches on the low-side MOSFET to discharge the output current to the regulation level (within the Power Good window).

When operating in dual-channel mode, both channels have identical yet independent protection schemes, which means one channel is not affected when the other channel is in fault mode.

When operating in two-phase mode, only the FB1 pin is detected for overvoltage and undervoltage fault. Therefore both channels take action together during a fault.

7.3.10 Input Undervoltage Lockout (UVLO)

A dedicated UVLO pin allows the user to program the desired input turn-on threshold voltage. The diagram is shown in Figure 22. The desired input turn-on threshold can be calculated using Equation 6. The input turn off hysteresis can be calculated using Equation 7.

Figure 22. Input UVLO Diagram

Equation 6.

Equation 7.

7.3.11 Power Good

The TPS40322 provides an indication that output is good for each channel. This is an open-drain signal that pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include:

• Feedback voltage (V_FB) is more than ±12.5% from nominal
• Soft-start is active

7.3.12 Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of 150°C, the PWMs and the oscillators are turned off and HDRVs and LDRVs are driven low. When the junction cools to the required level (130°C typical), the PWM initiates soft start as during a normal power-up cycle.

7.3.13 Connection of Unused Pins

In some case, it is possible that some pins are not used. For example, if only channel 1 is used, then pins for channel 2 need to be properly connected as well. The unused pin connections are summarized in Table 2.