SLUSAF8E July   2011  – January 2016 TPS40322

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Reference
      2. 7.3.2  Output Voltage Setting
      3. 7.3.3  Input Voltage Feedforward
      4. 7.3.4  Current Sensing
      5. 7.3.5  Overcurrent Protection
      6. 7.3.6  Two-Phase Mode, Remote Sense Amplifier, and Current Sharing Loop
      7. 7.3.7  Start-Up and Shutdown
        1. 7.3.7.1 Start-Up Sequence
        2. 7.3.7.2 Prebiased Output Start-Up
        3. 7.3.7.3 Shutdown
      8. 7.3.8  Switching Frequency and Master or Slave Synchronization
      9. 7.3.9  Overvoltage and Undervoltage Fault Protection
      10. 7.3.10 Input Undervoltage Lockout (UVLO)
      11. 7.3.11 Power Good
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Connection of Unused Pins
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-Output Configuration from 12-V Nominal to 1.2-V and 1.8-V DC-to-DC Converter Using the TPS40322
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting a Switching Frequency
          2. 8.2.1.2.2  Inductor Selection (L1)
          3. 8.2.1.2.3  Output Capacitor Selection (C10 through C16)
          4. 8.2.1.2.4  Peak Current Rating of Inductor
          5. 8.2.1.2.5  Input Capacitor Selection (C3 through C6)
          6. 8.2.1.2.6  MOSFET Selection (Q1)
          7. 8.2.1.2.7  ILIM Resistor (R2)
          8. 8.2.1.2.8  Feedback Divider (R10, R14)
          9. 8.2.1.2.9  Compensation: (R11, R12, C17, C19, C21)
          10. 8.2.1.2.10 Boot-Strap Capacitor (C7)
          11. 8.2.1.2.11 General Device Components
            1. 8.2.1.2.11.1 Synchronization (SYNC Pin)
            2. 8.2.1.2.11.2 RT Resistor (R6)
            3. 8.2.1.2.11.3 Differential Amplifier Out (DIFFO Pin)
            4. 8.2.1.2.11.4 EN/SS Timing Capacitors (C8)
            5. 8.2.1.2.11.5 Power Good (PG1, PG2 Pins)
            6. 8.2.1.2.11.6 Phase Set (PHSET Pin)
            7. 8.2.1.2.11.7 UVLO Programming Resistors (R1 and R3)
            8. 8.2.1.2.11.8 VDD Bypass Capacitor (C2)
            9. 8.2.1.2.11.9 VBP6 Bypass Capacitor (C18)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Phase, Single Output Configuration from 12-V nominal to 1.2-V DC-to-DC Converter Using the TPS40322
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage
      2. 10.1.2 Device Peripheral
      3. 10.1.3 Thermal Pad Layout
    2. 10.2 Layout Example
    3. 10.3 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.