SLUS930D April   2011  – November  2016 TPS40400

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting
      2. 7.3.2 Input Voltage Feedforward
      3. 7.3.3 Output Current Limit and Warning
      4. 7.3.4 Linear Regulators
      5. 7.3.5 PMBus Address
      6. 7.3.6 PMBus Connections
      7. 7.3.7 PMBus Functionality and Additional Set-Up
        1. 7.3.7.1  Data Format
        2. 7.3.7.2  Output Voltage Adjustment
        3. 7.3.7.3  Overcurrent Threshold
        4. 7.3.7.4  Output Current Reading
        5. 7.3.7.5  Soft-Start Time
        6. 7.3.7.6  Power Good
        7. 7.3.7.7  Undervoltage Lockout (UVLO)
        8. 7.3.7.8  Output Overvoltage and Undervoltage Thresholds
        9. 7.3.7.9  Programmable Fault Responses
        10. 7.3.7.10 User Data and Adjustable Anti-Cross-Conduction Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation with CNTL Signal Control
      3. 7.4.3 Operation with OPERATION Control
      4. 7.4.4 Operation with CNTL and OPERATION Control
      5. 7.4.5 Operation without CNTL or OPERATION Control
      6. 7.4.6 Operation with Output Trim and Margin
    5. 7.5 Programming
      1. 7.5.1 Supported PMBus Commands
    6. 7.6 Register Maps
      1. 7.6.1  OPERATION (01h)
        1. 7.6.1.1 On
        2. 7.6.1.2 Margin
      2. 7.6.2  ON_OFF_CONFIG (02h)
        1. 7.6.2.1 Pu
        2. 7.6.2.2 Cmd
        3. 7.6.2.3 Cpr
        4. 7.6.2.4 Pol
        5. 7.6.2.5 Cpa
      3. 7.6.3  CLEAR_FAULTS (03h)
      4. 7.6.4  WRITE_PROTECT (10h)
      5. 7.6.5  STORE_DEFAULT_ALL (11h)
      6. 7.6.6  RESTORE_DEFAULT_ALL (12h)
      7. 7.6.7  STORE_DEFAULT_CODE (13h)
      8. 7.6.8  RESTORE_DEFAULT_CODE (14h)
      9. 7.6.9  VOUT_MODE (20h)
        1. 7.6.9.1 Mode
        2. 7.6.9.2 Exponent
      10. 7.6.10 VOUT_TRIM (22h)
      11. 7.6.11 VOUT_MARGIN_HIGH (25h)
      12. 7.6.12 VOUT_MARGIN_LOW (26h)
      13. 7.6.13 VOUT_SCALE_LOOP (29h)
        1. 7.6.13.1 Exponent
        2. 7.6.13.2 Mantissa
      14. 7.6.14 FREQUENCY_SWITCH (33h)
        1. 7.6.14.1 Exponent
        2. 7.6.14.2 Mantissa
      15. 7.6.15 VIN_ON (35h)
        1. 7.6.15.1 Exponent
        2. 7.6.15.2 Mantissa
      16. 7.6.16 VIN_OFF (36h)
        1. 7.6.16.1 Exponent
        2. 7.6.16.2 Mantissa
      17. 7.6.17 IOUT_CAL_GAIN (38h)
        1. 7.6.17.1 Exponent
        2. 7.6.17.2 Mantissa
      18. 7.6.18 IOUT_CAL_OFFSET (39h)
        1. 7.6.18.1 Exponent
        2. 7.6.18.2 Mantissa
      19. 7.6.19 VOUT_OV_FAULT_LIMIT (40h)
      20. 7.6.20 VOUT_OV_FAULT_RESPONSE (41h)
        1. 7.6.20.1 RSP[1:0]
        2. 7.6.20.2 RS[2:0]
      21. 7.6.21 VOUT_UV_FAULT_LIMIT (44h)
      22. 7.6.22 VOUT_UV_FAULT_RESPONSE (45h)
        1. 7.6.22.1 RSP[1:0]
        2. 7.6.22.2 RS[2:0]
      23. 7.6.23 IOUT_OC_FAULT_LIMIT (46h)
        1. 7.6.23.1 Exponent
        2. 7.6.23.2 Mantissa
      24. 7.6.24 IOUT_OC_FAULT_RESPONSE (47h)
        1. 7.6.24.1 RSP[1:0]
        2. 7.6.24.2 RS[2:0]
      25. 7.6.25 IOUT_OC_WARN_LIMIT (4Ah)
        1. 7.6.25.1 Exponent
        2. 7.6.25.2 Mantissa
      26. 7.6.26 OT_FAULT_RESPONSE (50h)
        1. 7.6.26.1 OTF_RS
      27. 7.6.27 POWER_GOOD_ON (5Eh)
      28. 7.6.28 POWER_GOOD_OFF (5Fh)
      29. 7.6.29 TON_RISE (61h)
        1. 7.6.29.1 Exponent
        2. 7.6.29.2 Mantissa
      30. 7.6.30 STATUS_BYTE (78h)
      31. 7.6.31 STATUS_WORD (78h)
      32. 7.6.32 STATUS_VOUT (7Ah)
      33. 7.6.33 STATUS_IOUT (7Bh)
      34. 7.6.34 STATUS_TEMPERATURE (7Dh)
      35. 7.6.35 STATUS_CML (7Eh)
      36. 7.6.36 READ_VIN (88h)
        1. 7.6.36.1 Exponent
        2. 7.6.36.2 Mantissa
      37. 7.6.37 READ_VOUT (8Bh)
        1. 7.6.37.1 Exponent
        2. 7.6.37.2 Mantissa
      38. 7.6.38 READ_IOUT (8Ch)
        1. 7.6.38.1 Exponent
        2. 7.6.38.2 Mantissa
      39. 7.6.39 PMBUS_REVISION (98h)
      40. 7.6.40 MFR_VIN_MIN (A0h)
        1. 7.6.40.1 Exponent
        2. 7.6.40.2 Mantissa
      41. 7.6.41 MFR_VIN_MAX (A1h)
        1. 7.6.41.1 Exponent
        2. 7.6.41.2 Mantissa
      42. 7.6.42 MFR_VOUT_MIN (A4h)
        1. 7.6.42.1 Exponent
        2. 7.6.42.2 Mantissa
      43. 7.6.43 MFR_VOUT_MAX (A5h)
        1. 7.6.43.1 Exponent
        2. 7.6.43.2 Mantissa
      44. 7.6.44 MFR_SPECIFIC_00 (D0h)
        1. 7.6.44.1 Dead-Time Control Setting (DTC)
        2. 7.6.44.2 WPE
      45. 7.6.45 MFR_SPECIFIC_01 (D1h)
      46. 7.6.46 MFR_SPECIFIC_02 (D2h)
      47. 7.6.47 MFR_SPECIFIC_03 (D3h)
      48. 7.6.48 MFR_SPECIFIC_04 (D4h)
      49. 7.6.49 MFR_SPECIFIC_05 (D5h)
      50. 7.6.50 MFR_SPECIFIC_06 (D6h)
      51. 7.6.51 MFR_SPECIFIC_07 (D7h)
      52. 7.6.52 MFR_SPECIFIC_44 (FCh)
        1. 7.6.52.1 Identifier Code
        2. 7.6.52.2 Revision Code
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS40400 12-V Input, 1.2-V Output, 20-A (maximum) Output Current ConverterAdded Design Example 1
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Design Example List of Materials
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting a Switching Frequency
          2. 8.2.1.2.2  Output Inductor, LOUT
          3. 8.2.1.2.3  Output Capacitance, COUT
          4. 8.2.1.2.4  The Resistive Component of Output Ripple
          5. 8.2.1.2.5  Peak Current Rating of the Inductor
          6. 8.2.1.2.6  Input Capacitance, CIN
          7. 8.2.1.2.7  Switching MOSFETs, QHS and QLS
          8. 8.2.1.2.8  Device Addressing, RADDR0 and RADDR1
          9. 8.2.1.2.9  Current Sense Flter, R16 and C17
          10. 8.2.1.2.10 Voltage Decoupling Capacitors, CBP3, CBP6, and CVDD
          11. 8.2.1.2.11 Bootstrap Capacitor, C9
          12. 8.2.1.2.12 Snubber R12 and C16
          13. 8.2.1.2.13 Loop Compensaton Components
          14. 8.2.1.2.14 Output Voltage Set Point, RBIAS
          15. 8.2.1.2.15 Remote Sensing
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TPS40400 12-V Input 5-V Output, 5-A (Maximum) Output Current Converter Design Example 2Added Design Example 2
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 List of Materials
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Internal Configuration
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHL Package
24-Pin VQFN
Bottom View
TPS40400 pinout_lus930.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
ADDR0 21 I Low-order address pin for PMBus address configuration. One of eight resistor values must be connected from this pin to SGND to select the low-order octal digit in the PMBus address.
ADDR1 22 I High-order address pin for PMBus address configuration. One of eight resistor values must be connected from this pin to SGND to select the high-order octal digit in the PMBus address.
BOOT 18 I Gate drive voltage for the high-side, N-channel MOSFET. A capacitor (100-nF) typical must be connected between this pin and SW.
BP3 13 O Bypass pin for the internal regulator that supplies power to the internal controls of the device. Normal regulation voltage is 3.3 V. Connect a capacitor with a value of 100-nF or larger from this pin to GND.
BP6 14 O Bypass pin for the internal regulator that supplies power to the gate drivers. Normal regulation voltage is 6.5 V. Connect a capacitor with a value of 1-μF or larger from this pin to GND.
CLK 1 I Clock input for the PMBus interface
CNTL 2 I Logic level input that controls the start-up and shutdown of the converter. PMBus options determine exact functionality.
COMP 6 O Output of the error amplifier. Used for control loop compensation.
DATA 24 I/O Data I/O for the PMBus interface
DIFFO 8 O Output of the unity gain remote voltage sense amplifier. Typically connected to the voltage divider on FB
FB 7 I Inverting input to the error amplifier. A voltage divider is connected to from the DIFFO pin to the FB pin to sense the output voltage.
GND 15 – Common connection for the device. This pin should connect to the thermal pad under the device package and to the power stage ground, preferably close to the source of the low-side or rectifier MOSFET. Connections should be arranged so that no high-power level currents flow across the pad connected to the thermal pad on the underside of the device.
HDRV 19 O Gate drive signal to the high-side MOSFET
ISNS– 11 I Inverting input to the current sense amplifier
ISNS+ 12 I Noninverting input to the current sense amplifier
LDRV 16 O Output used to drive the gate of the low-side or rectifier MOSFET.
PGOOD 3 O Power good output. This is an open-drain output that pulls low when any fault condition exists within the device or when the device is not operating within a user-selectable operating range of the nominal output voltage of the converter.
SGND PAD – Signal ground for the device. Connect the ground of signal level circuits to this pin. Connections should be arranged so that power level currents do not flow in the pad attached to the thermal plane or in the SGND portion of the circuit.
SMBALRT 23 O Output used to signal that PMBus host that the device needs attention.
SW 17 I This is the common connection for the flying high-side MOSFET driver and also serve as a sense line for the adaptive anti-cross-conduction circuitry
SYNC 4 I Logic level input to the oscillator inside the device. The oscillator resets on the rising edge of a pulse train applied to this pin and begin a new switching cycle.
TRACK 5 I Analog input to the noninverting side of the control loop error amplifier. The error amplifier has three inputs (voltage reference, TRACK and soft-start time) to its + side, and the lowest voltage applied to these three inputs dominate and control the output voltage of the whole converter. This pin is to allow the user to configure a voltage divider that allows the device output follow an external reference voltage during start-up.
VDD 20 I Input power connection for the device. This pin requires a supply voltage of between 3 V to 20 V.
VSNS+ 9 I Noninverting input to the unity gain remote voltage sense amplifier.
VSNS– 10 I Inverting input to the unity gain remote voltage sense amplifier.
(1) I = Input, O = Output, P = Supply, G = Ground