SLUSAQ4G October   2011  – September 2022 TPS40422

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PMBus Interface Protocol General Description
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Output Voltage
      4. 8.3.4  Voltage Feed Forward
      5. 8.3.5  Current Sensing
      6. 8.3.6  Overcurrent Protection
      7. 8.3.7  Current Sharing
      8. 8.3.8  Linear Regulators
      9. 8.3.9  BP Switch-over
      10. 8.3.10 Switching Frequency Setting
      11. 8.3.11 Switching Node and BOOT Voltage
      12. 8.3.12 Reading the Output Current
      13. 8.3.13 Soft-Start Time
      14. 8.3.14 Turn-On/Turn-Off Delay and Sequencing
      15. 8.3.15 Pre-Biased Output Start-Up
      16. 8.3.16 Undervoltage Lockout
      17. 8.3.17 Overvoltage and Undervoltage Fault Protection
      18. 8.3.18 Power Good
      19. 8.3.19 Overtemperature Fault Protection
      20. 8.3.20 Thermal Shutdown
      21. 8.3.21 Programmable Fault Responses
      22. 8.3.22 User Data
      23. 8.3.23 Adjustable Anti-Cross Conduction Delay
      24. 8.3.24 Connection of Unused Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Signal
      2. 8.4.2 OPERATION Command
      3. 8.4.3 Control Signal and OPERATION Command
      4. 8.4.4 Two-Phase Mode Operation
    5. 8.5 Programming
      1. 8.5.1 Supported PMBus Commands
        1. 8.5.1.1 PMBus Address
        2. 8.5.1.2 PMBus Connections
        3. 8.5.1.3 PMBus Data Format
        4. 8.5.1.4 PMBus Interface Output Voltage Adjustment
        5. 8.5.1.5 53
    6. 8.6 Register Maps
      1. 8.6.1 Supported Commands
        1. 8.6.1.1  PAGE (00h)
        2. 8.6.1.2  OPERATION (01h)
          1. 8.6.1.2.1 On
          2. 8.6.1.2.2 Margin
        3. 8.6.1.3  ON_OFF_CONFIG (02h)
          1. 8.6.1.3.1 pu
          2. 8.6.1.3.2 cmd
          3. 8.6.1.3.3 CPR
          4. 8.6.1.3.4 pol
          5. 8.6.1.3.5 CPA
        4. 8.6.1.4  CLEAR_FAULTS (03h)
        5. 8.6.1.5  WRITE_PROTECT (10h)
          1. 8.6.1.5.1 bit5
          2. 8.6.1.5.2 bit6
          3. 8.6.1.5.3 bit7
        6. 8.6.1.6  STORE_USER_ALL (15h)
        7. 8.6.1.7  RESTORE_USER_ALL (16h)
        8. 8.6.1.8  CAPABILITY (19h)
        9. 8.6.1.9  VOUT_MODE (20h)
          1. 8.6.1.9.1 Mode:
          2. 8.6.1.9.2 Exponent
        10. 8.6.1.10 VIN_ON (35h)
          1. 8.6.1.10.1 Exponent
          2. 8.6.1.10.2 Mantissa
        11. 8.6.1.11 VIN_OFF (36h)
          1. 8.6.1.11.1 Exponent
          2. 8.6.1.11.2 Mantissa
        12. 8.6.1.12 IOUT_CAL_GAIN (38h)
          1. 8.6.1.12.1 Exponent
          2. 8.6.1.12.2 Mantissa
        13. 8.6.1.13 IOUT_CAL_OFFSET (39h)
          1. 8.6.1.13.1 Exponent
          2. 8.6.1.13.2 Mantissa
        14. 8.6.1.14 IOUT_OC_FAULT_LIMIT (46h)
          1. 8.6.1.14.1 Exponent
          2. 8.6.1.14.2 Mantissa
        15. 8.6.1.15 IOUT_OC_FAULT_RESPONSE (47h)
          1. 8.6.1.15.1 RS[2:0]
        16. 8.6.1.16 IOUT_OC_WARN_LIMIT (4Ah)
          1. 8.6.1.16.1 Exponent
          2. 8.6.1.16.2 Mantissa
        17. 8.6.1.17 OT_FAULT_LIMIT (4Fh)
          1. 8.6.1.17.1 Exponent
          2. 8.6.1.17.2 Mantissa
        18. 8.6.1.18 OT_WARN_LIMIT (51h)
          1. 8.6.1.18.1 Exponent
          2. 8.6.1.18.2 Mantissa
        19. 8.6.1.19 TON_RISE (61h)
          1. 8.6.1.19.1 Exponent
          2. 8.6.1.19.2 Mantissa
        20. 8.6.1.20 STATUS_BYTE (78h)
        21. 8.6.1.21 STATUS_WORD (79h)
        22. 8.6.1.22 STATUS_VOUT (7Ah)
        23. 8.6.1.23 STATUS_IOUT (7Bh)
        24. 8.6.1.24 STATUS_TEMPERATURE (7Dh)
        25. 8.6.1.25 STATUS_CML (7Eh)
        26. 8.6.1.26 STATUS_MFR_SPECIFIC (80h)
        27. 8.6.1.27 READ_VOUT (8Bh)
        28. 8.6.1.28 READ_IOUT (8Ch)
          1. 8.6.1.28.1 Exponent
          2. 8.6.1.28.2 Mantissa
        29. 8.6.1.29 READ_TEMPERATURE_2 (8Eh)
          1. 8.6.1.29.1 Exponent
          2. 8.6.1.29.2 Mantissa
        30. 8.6.1.30 PMBUS_REVISION (98h)
        31. 8.6.1.31 MFR_SPECIFIC_00 (D0h)
        32. 8.6.1.32 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
        33. 8.6.1.33 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
        34. 8.6.1.34 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
        35. 8.6.1.35 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h)
        36. 8.6.1.36 126
        37. 8.6.1.37 SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h)
        38. 8.6.1.38 128
        39. 8.6.1.39 OPTIONS (MFR_SPECIFIC_21) (E5h)
        40. 8.6.1.40 DEVICE_CODE (MFR_SPECIFIC_44) (FCh)
          1. 8.6.1.40.1 Identifier Code
          2. 8.6.1.40.2 Revision Code
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dual-Output Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Step 1: Inductor Selection
          3. 9.2.1.2.3 Step 2: Output Capacitor Selection
          4. 9.2.1.2.4 Step 3: Input Capacitance Selection
          5. 9.2.1.2.5 Step 4: MOSFET Selection
          6. 9.2.1.2.6 Step 5: Snubber Circuit Design
          7. 9.2.1.2.7 Step 6: Soft-Start Time
          8. 9.2.1.2.8 Step 7: Peripheral Component Design
            1. 9.2.1.2.8.1 RT (Pin 1) Switching Frequency Setting
            2. 9.2.1.2.8.2 FB1 (Pin 2) and FB2 (Pin 8) Output Voltage Setting
            3. 9.2.1.2.8.3 Compensation Network Using COMP1 (Pin 3) , COMP2 (Pin 7), FB1 (Pin 2) FB2 DIFFO1 (Pin 8) (Pin 39)
            4. 9.2.1.2.8.4 Remote Sensing Using VSNS1 (Pin 37), GSNS1 (Pin 38) , VSNS2 (Pin 15), and GSNS2 (Pin 14)
            5. 9.2.1.2.8.5 Temperate Sensing Using TSNS1 (Pin36) and TSNS2 (Pin 16)
            6. 9.2.1.2.8.6 Current Sensing Network Design Using CS1P (Pin 34), CS1N (Pin 35) , CS2P (Pin 18), and CS2N (Pin 17)
            7. 9.2.1.2.8.7 PMBus Address ADDR1 (Pin 9) , and ADDR0 (Pin 10)
            8. 9.2.1.2.8.8 Voltage Decoupling Capacitors
              1. 9.2.1.2.8.8.1  VDD (Pin 31)
              2. 9.2.1.2.8.8.2  BP3 (Pin 32)
              3. 9.2.1.2.8.8.3  BNEXT (Pin 24)
              4. 9.2.1.2.8.8.4  BP6 (Pin 25)
              5. 9.2.1.2.8.8.5  Power Good PGOOD1 (Pin 33), PGOOD2 (Pin 19)
              6. 9.2.1.2.8.8.6  Bootstrap Capacitors BOOT1 (Pin 30), and BOOT2 (Pin 20)
              7. 9.2.1.2.8.8.7  High-Side MOSFET (Gate) Resistor
              8. 9.2.1.2.8.8.8  Synchronization Setting SYNC (Pin 40)
              9. 9.2.1.2.8.8.9  BP6 (Pin 25)
              10. 9.2.1.2.8.8.10 DIFFO (Pin 39)
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines
      2. 11.1.2 MOSFET Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.8.8.7 High-Side MOSFET (Gate) Resistor

In order to reduce the voltage spike on switching node further, it is recommended to add a high-side gate resistor and use a Schottky diode in parallel with the resistor (connect anode to gate, and connect cathode to driver) to maintain fast turn off. This application requires a Schottky diode If the gate resistor is more than 3 Ω, so as not to interfere with the anti-cross-conduction circuit.

The MOSFET resistor and Schottky diode are not presented on design sample, but they are recommended if the voltage spike on switching node or BOOT pin is above the absolute maximum rating and need to be reduced to avoid device failure.