SLUSBV0 Data sheet

SLUSBV0A May 2014 – JULY 2014 TPS40428

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RHA|40
- MPQF135D

Thermal pad, mechanical data (Package|Pins)

RHA|40
- QFND115P

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage range	VDD	–0.3	22	V
	CS1N, CS1P, CS2N, CS2P, GSNS1, GSNS2, ISH1, ISH2, PHSET, PMBDATA, PMBCLK, SMBALERT, SYNC, VSNS1, VSNS2	–0.3	5.5
	AVSDATA, AVSCLK, TSNS1, TSNS2	–0.3	3.6
	CNTL1, CNTL2, FB1, FB2	–0.3	7
Output voltage range	ADDR0, ADDR1, RT, BP3	–0.3	3.6	V
Output voltage range	BP5, COMP1, COMP2, DIFFO1, FLT1, FLT2, PG1, PG2, PWM1, PWM2	–0.3	7	V
Operating junction temperature, T_J		–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	155	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2	2	kV
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–1.5	1.5	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Input operating voltage	4.5	20	V
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS40428	UNIT
THERMAL METRIC⁽¹⁾		QFN (40 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	27.8	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	17.2
θ_JB	Junction-to-board thermal resistance	4.8
R_ψJT	Junction-to-top characterization parameter	0.2
R_ψJB	Junction-to-board characterization parameter	4.8
R_θJCbot	Junction-to-case (bottom) thermal resistance	1.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

T_J = –40ºC to 125ºC, V_IN = V_VDD = 12 V, R_RT valued to produce a switching frequency (f_SW) of 500 kHz, all parameters at zero power dissipation (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_VDD	Input supply voltage range		4.5		20	V
I_VDD	Input operating current	Switching, no driver load, smart-power mode		17.3		mA
I_VDD	Input operating current	Not switching, smart-power mode		15.9		mA
UVLO
V_IN(on)	Input turn-on voltage⁽³⁾	Default settings	4	4.25	4.5	V
V_IN(off)	Input turn-off voltage⁽³⁾	Default settings	3.8	4	4.2	V
V_INON(rng)	Programmable range for turn on voltage		4.25		16	V
V_INOFF(rng)	Programmable range for turn off voltage		4		15.75	V
ERROR AMPLIFIER
V_FB	Feedback pin voltage	–40°C ≤ T_J ≤ 125°C	597	600	603	mV
A_OL	Open-loop gain⁽¹⁾		80			dB
G_BWP	Gain bandwidth product⁽¹⁾		50			MHz
I_FB	FB pin bias current (out of pin)	V_FB = 0.6 V			100	nA
I_COMP	Sourcing	V_FB = 0 V	1			mA
I_COMP	Sinking	V_FB = 1 V	1			mA
BP5 REGULATOR
V_BP5	Output voltage	I_BP5 = 10 mA	4.5	5	5.5	V
V_BP5	Dropout voltage	V_VIN – V_BP5, V_VDD = 4.5 V, I_BP5 = 25 mA			400	mV
I_BP5	Output current	V_VDD = 12 V	40			mA
V_BP5UV	Regulator UVLO voltage⁽¹⁾		3.3	3.55	3.8	V
V_BP5UV(hyst)	Regulator UVLO voltage hysteresis⁽¹⁾			300		mV
BP3 REGULATOR
V_BP3	Output voltage	V_VDD = 4.5 V, I_BP3 ≤ 5 mA	3.1	3.3	3.5	V
OSCILLATOR AND RAMP GENERATOR
ƒ_SW	Adjustment range⁽¹⁾		200		1500	kHz
	Switching frequency⁽⁴⁾	R_RT = 100 kΩ	180	200	220	kHz
	Switching frequency⁽⁴⁾	R_RT = 40 kΩ	450	500	550
	Switching frequency⁽⁴⁾	R_RT = 13 kΩ	1230	1370	1500
V_RAMP	Ramp amplitude (peak-to-peak)			V_VDD/10		V
V_VAL	Valley voltage			1.22		V
SYNCHRONIZATION
V_SYNCH	SYNC high-level threshold⁽²⁾		2			V
V_SYNCL	SYNC low-level threshold⁽²⁾				0.8	V
t_SYNC	Minimum SYNC pulse width⁽¹⁾				100	ns
ƒ_SYNC	Maximum PWM frequency for SYNC⁽¹⁾		1500			kHz
	Minimum PWM frequency for SYNC⁽¹⁾				200	kHz
	SYNC frequency range (increase from nominal oscillator frequency)⁽¹⁾		–20%		20%
PWM
V_OH(pwm)	PWM high-level output voltage	I_LOAD = 500 µA	4.5			V
V_OL(pwm)	PWM low-level output voltage	I_LOAD = 500 µA			0.5	V
t_OFF(min)	Minimum off-time			100		ns
t_ON(min)	Minimum pulse			90		ns
SOFT-START
t_SS	Soft-start time⁽⁷⁾	Factory default settings		2.7		ms
	Programmable range⁽¹⁾		0.6		9	ms
	Accuracy over range⁽¹⁾		–15%		15%
t_ON(dly)	Turn-on delay time⁽¹⁾	Factory default settings		0		ms
t_OFF(dly)	Turn-off delay time⁽¹⁾	Factory default settings		0		ms
REMOTE SENSE AMPLIFIER
BW	Closed-loop bandwidth⁽¹⁾		2			MHz
V_DIFFO(max)	Maximum DIFFO output voltage				4.7	V
V_DIFFO(err)	Error voltage from DIFFO1 to (V_SNS1– G_SNS1)	(V_SNS1– G_SNS1) = 1.0 V	–6		6	mV
V_DIFFO(err)	Error voltage from DIFFO1 to (V_SNS1– G_SNS1)	(V_SNS1– G_SNS1) = 3.6 V	–19		19
I_DIFFO	Sourcing		1			mA
I_DIFFO	Sinking		1			mA
CURRENT SENSING AMPLIFIER
V_CS(mg)	Differential input voltage linear range	(V_CSxP – V_CSxN), non-smart power mode	0		60	mV
V_CS(mg)	Differential input voltage linear range	(V_CSxP – V_CSxN), smart power mode	0		600	mV
V_CS(cmr)	Input common-mode range	Non-smart power mode	0		3.6	V
V_CS(cm)	Input common-mode voltage	Smart power mode		1.24		V
A_CS	Current sensing gain	CHx_CSGAIN_SEL= 20 V/V⁽⁵⁾, non-smart power mode		10		V/V
A_CS	Current sensing gain	CHx_CSGAIN_SEL= 20 V/V⁽⁵⁾, smart power mode		1		V/V
f_CO	Closed loop bandwidth⁽¹⁾			0.66		MHz
V_CS(chch)	Amplifier output difference between two channels⁽⁶⁾	I_PHASE = 20 A, IOUT_CAL_GAIN = 0.503 mΩ	–6%		6%
CURRENT LIMIT
t_OFF(oc)	Off-time between restart attempts	Hiccup mode		7 × t_SS		ms
I_OC(flt)	Output peak current overcurrent fault threshold	Factory default settings		40		A
I_OC(flt)	Output peak current overcurrent fault threshold	Programmable range	3		50	A
I_OC(warn)	Output peak current overcurrent warning threshold	Factory default settings		37		A
I_OC(warn)	Output peak current overcurrent warning threshold	Programmable range	2		49	A
I_OC(acc)	Output peak current overcurrent fault accuracy	I_OUT = 40 A, IOUT_CAL_GAIN = 0.503 mΩ	–10%		10%
I_OC(acc)	Output peak current overcurrent warning accuracy	I_OUT = 37 A, IOUT_CAL_GAIN = 0.503 mΩ	–10%		10%
PGOOD
V_FBPGH	FB PGOOD high threshold	Factory default settings		642		mV
V_FBPGL	FB PGOOD low threshold	Factory default settings		558		mV
V_PG(acc)	PGOOD accuracy over range		–4%		4%
V_pg(hyst)	FB PGOOD hysteresis voltage		15	28	45	mV
R_PGOOD	PGOOD pull-down resistance	V_FB = 0 V, I_PGOOD = 5 mA		50		Ω
I_PGOOD(lk)	PGOOD pin leakage current	V_FB = 600 mV, V_PGOOD = 5 V			20	µA
t_PGDELAY	PGOOD delay time after soft-start sequence is complete	Factory default settings		2		ms
OUTPUT OVERVOLTAGE/UNDERVOLTAGE
V_FBOV	FB pin over voltage threshold	Factory default settings		700		mV
V_FBUV	FB pin under voltage threshold	Factory default settings		528		mV
V_UVOV(acc)	FB UV/OV accuracy over range		–4%		4%
OUTPUT VOLTAGE TRIMMING AND MARGINING
V_FBTM(step)	Resolution of FB steps with trim and margin			2		mV
t_FBTM(step)	Transition time per trim or margin step	After soft-start time		30		µs
V_FBTM(max)	Maximum FB voltage with trim or margin only			660		mV
V_FBTM(min)	Minimum FB voltage with trim or margin only			480		mV
V_FBTM(rng)	FB voltage range with trim and margin combined		420		660	mV
V_FBMH	Margin high FB pin voltage	Factory default settings		660		mV
V_FBML	Margin low FB pin voltage	Factory default settings		540		mV
OUTPUT VOLTAGE AT AVS MODE
V_FBAVS(step)	Resolution of FB steps at AVS mode			2		mV
V_FBAVS(max)	Maximum FB voltage at AVS mode			1.5		V
V_FBAVS(min)	Minimum FB voltage at AVS mode			500		mV
AVS INTERFACE
V_VIO	ASIC I/O voltage⁽¹⁾		1.8		2.5	V
V_IH(avs)	High-level input voltage, AVSCLK, AVSDATA	V_VIO = 2.5 V	1.75			V
V_IH(avs)	High-level input voltage, AVSCLK, AVSDATA	V_VIO = 1.8 V	1.26			V
V_IL(avs)	Low-level input voltage, AVSCLK, AVSDATA	V_VIO = 2.5 V			0.75	V
V_IL(avs)	Low-level input voltage, AVSCLK, AVSDATA	V_VIO = 1.8 V			0.54	V
I_IH(avs)	High-level input current, AVSCLK, AVSDATA⁽¹⁾		–50		50	µA
I_IL(avs)	Low-level input current, AVSCLK, AVSDATA⁽¹⁾		–50		50	µA
f_AVS	AVS clock frequency range		10		30	MHz
MEASUREMENT SYSTEM
M_VOUT(rng)	V_OUT measurement range		0.5		3.6	V
M_VOUT(acc)	V_OUT measurement accuracy⁽⁶⁾	V_OUT = 1 V, 0°C ≤ T_J ≤ 125°C	–0.8%		0.8%
M_IOUT(rng)	I_OUT measurement range⁽⁹⁾		0		50	A
M_IOUT(acc)	I_OUT measurement accuracy⁽⁶⁾	I_OUT ≥ 20 A, IOUT_CAL_GAIN = 0.503 mΩ, 0°C ≤ T_J ≤ 125°C, smart power mode	–640		640	mA
PMBus INTERFACE⁽⁸⁾
V_IH	High-level input voltage, CLK, DATA, CNTL		2.1			V
V_IL	Low-level input voltage, CLK, DATA, CNTL				0.8	V
I_IH	High-level input current, CLK, DATA, CNTL	Pin voltage = 3.3 V	–10		10	µA
I_IL	Low-level input current, CLK, DATA, CNTL	Pin voltage = 0 V	–10		10	µA
V_OL	Low-level output voltage, DATA, SMBALRT	I_OUT = 4 mA			0.4	V
I_OH	High-level output open drain leakage current, DATA, SMBALRT	V_OUT = V_BP5	0		10	µA
I_OL	Low-level output open drain current, DATA, SMBALRT		4			mA
C_OUT	Pin capacitance, CLK, DATA⁽¹⁾				1	pF
f_PMB	PMBus operating frequency range	Slave mode	10		400	kHz
t_BUF	Bus free time between START and STOP⁽¹⁾		1.3			µs
t_HD:STA	Hold time after repeated START⁽¹⁾		0.6
t_SU:STA	Repeated START set-up time⁽¹⁾		0.6
t_SU:STO	STOP setup time⁽¹⁾		0.6
t_HD:DAT	Data hold time⁽¹⁾	Receive mode	0			ns
t_HD:DAT	Data hold time⁽¹⁾	Transmit mode	300
t_SU:DAT	Data setup time⁽¹⁾		100
t_TIMEOUT	Error signal/detect⁽¹⁾		25		35	ms
t_LOW:MEXT	Cumulative clock low master extend time⁽¹⁾				10	ms
t_LOW:SEXT	Cumulative clock low slave extend time⁽¹⁾				25	ms
t_LOW	Clock low time⁽¹⁾		1.3			µs
t_HIGH	Clock high time⁽¹⁾		0.6			µs
t_FALL	CLK/DATA fall time⁽¹⁾				300	ns
t_RISE	CLK/DATA rise time⁽¹⁾				300	ns
t_RETENTION	Retention of configuration parameters⁽¹⁾	T_J = 25°C	100			Year
Write_cycles	Number of nonvolatile erase/write cycles⁽¹⁾	T_J = 25°C	20			K cycle
PMBus ADDRESSING
I_ADD	Address pin bias current		8.775	9.75	10.725	µA
INITIALIZATION TIME
t_INI	Initialization time after BP3 voltage is ready⁽¹⁾			1		ms
TEMPERATURE SENSE AND THERMAL SHUTDOWN
T_SD	Junction shutdown temperature⁽¹⁾			160		°C
T_HYST	Thermal shutdown hysteresis⁽¹⁾			20		°C
I_TSNS(ratio)	Ratio of bias current flowing out of TSNS pin, state 2 to state 1	Non-smart power mode	9.7	10	10.3
I_TSNS(1)	State 1 current out of TSNS pin	Non-smart power mode		10		µA
I_TSNS(2)	State 2 current out of TSNS pin	Non-smart power mode		100		µA
T_SNS(acc)	External temperature sense accuracy⁽⁶⁾	–40°C ≤ T_SNS ≤ 125°C, Non-smart power mode	–4.5		4.5	°C
T_SNS(acc)	External temperature sense accuracy⁽⁶⁾	–40°C ≤ T_SNS ≤ 125°C, Smart power mode	–3		3	°C
T_OT(flt)	Overtemperature fault limit⁽¹⁾	Factory default settings		145		°C
T_OT(flt)	OT fault limit range⁽¹⁾		120		165	°C
T_OT(warn)	Overtemperature warning limit⁽¹⁾	Factory default settings		125		°C
T_OT(warn)	OT warning limit range⁽¹⁾		100		140	°C
T_OT(step)	OT fault/warning step			1		°C
T_OT(hys)	OT fault/warning hysteresis⁽¹⁾			20		°C

(1) Specified by design. Not production tested.

(2) The external SYNC pin signal must be a square waveform with 50% duty cycle.

(3) Hysteresis of at least 150 mV is specified by design.

(4) Apply to 1-,2- or 4-phase operation. For 3-phase operation, the switching frequency is 33% higher than the value in the table.

(5) Refer to PMBus command MFR_SPECIFIC_21 (OPTIONS) (E5h) section.

(6) Performance verified under application conditions.

(7) The soft-start time is the time that the internal reference voltage rises from 0 V to 600 mV.

(8) The device supports both 100-kHz and 400-kHz bus speeds. The PMBus timing parameters in this table is for operation at 400 kHz. If the PMBus operating frequency is 100 kHz, refer to SMBus specification for timing parameters.

(9) The actual measurement range is limited by IOUT_CAL_GAIN command. See the IOUT_CAL_GAIN (38h) section.