SLVSC16B August   2013  – July 2016 TPS43330A-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Controller
      2. 7.3.2 Gate-Driver Supply (VREG, EXTSUP)
      3. 7.3.3 External P-Channel Drive (GC2) and Reverse Battery Protection
      4. 7.3.4 Undervoltage Lockout and Overvoltage Protection
      5. 7.3.5 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.4.1.1 Frequency Selection and External Synchronization
        2. 7.4.1.2 Enable Inputs
        3. 7.4.1.3 Feedback Inputs
        4. 7.4.1.4 Soft-Start Inputs
        5. 7.4.1.5 Current-Mode Operation
        6. 7.4.1.6 Current Sensing and Current Limit With Foldback
        7. 7.4.1.7 Slope Compensation
        8. 7.4.1.8 Power-Good Outputs and Filter Delays
        9. 7.4.1.9 Light-Load PFM Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Boost Component Selection
        2. 8.2.2.2  Boost Maximum Input Current IIN_MAX
        3. 8.2.2.3  Boost Inductor Selection, L
        4. 8.2.2.4  Inductor Ripple Current, IRIPPLE
        5. 8.2.2.5  Peak Current in Low-Side FET, IPEAK
        6. 8.2.2.6  Right Half-Plane Zero RHP Frequency, fRHP
        7. 8.2.2.7  Output Capacitor, COUTx
        8. 8.2.2.8  Bandwidth of Boost Converter, fC
        9. 8.2.2.9  Output Ripple Voltage Due to Load Transients, ∆VOUTx
        10. 8.2.2.10 Selection of Components for Type II Compensation
        11. 8.2.2.11 Input Capacitor, CIN
        12. 8.2.2.12 Output Schottky Diode D1 Selection
        13. 8.2.2.13 Low-Side MOSFET (BOT_SW3)
        14. 8.2.2.14 BuckA Component Selection
          1. 8.2.2.14.1 BuckA Component Selection
          2. 8.2.2.14.2 Current-Sense Resistor RSENSE
        15. 8.2.2.15 Inductor Selection L
        16. 8.2.2.16 Inductor Ripple Current IRIPPLE
        17. 8.2.2.17 Output Capacitor COUTA
        18. 8.2.2.18 Bandwidth of Buck Converter fC
        19. 8.2.2.19 Selection of Components for Type II Compensation
        20. 8.2.2.20 Resistor Divider Selection for Setting VOUTA Voltage
        21. 8.2.2.21 BuckB Component Selection
        22. 8.2.2.22 Resistor Divider Selection for Setting VOUT Voltage
        23. 8.2.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Example 1
      2. 8.3.2 Example 2
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Converter
      2. 10.1.2 Buck Converter
      3. 10.1.3 Other Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TPS43330A-Q1 includes two current-mode synchronous-buck controllers and a voltage-mode boost controller. The device is ideally suited as a preregulator stage with low IQ requirements and for applications that must operate during supply drops due to cranking events. The integrated boost controller allows the device to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. At light loads, the buck controllers enable to operate automatically in low-power mode, consuming just 30 μA of quiescent current.

The buck controllers have independent soft-start capability and power-good indicators. Current foldback in the buck controllers and cycle-by-cycle current limitation in the boost controller provide external MOSFET protection. The switching frequency is programable over 150 kHz to 600 kHz or is synchronized to an external clock in the same range.

7.2 Functional Block Diagram

TPS43330A-Q1 block_diagram_SLVSC16.gif

7.3 Feature Description

7.3.1 Boost Controller

The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit protection for the external N-channel MOSFET. The boost-controller switching-frequency setting is one-half of the buck-controller switching frequency. An internal resistor-divider network programmable to 7 V, 8.85 V, or 10 V sets the output voltage of the boost controller at the VIN pin, based on the low, open, or high status, respectively, of the DIV pin (see Table 1). The device does not recognize a change of the DIV setting while in the low-power mode.

Table 1. Output Voltage Settings

DIV SETTING BOOST OUTPUT VOLTAGE
Low 7 V
Open 8.85 V
High 10 V

The active-high ENC pin enables the boost controller, which is active when the input voltage at the VBAT pin has crossed the boost unlock threshold (VBOOST_UNLOCK) of 8.5 V at least once. A single high-to-low transition of VBAT below the boost-enable threshold (Vboost(x)-th) arms the boost controller, which starts switching as soon as VIN falls below the value set by the DIV pin, regulating the VIN voltage. Thus, the boost regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking pulse at VBAT.

A voltage at the DS pin exceeding 200 mV pulls the GC1 pin low, turning off the boost external MOSFET. Connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and ground achieves cycle-by-cycle overcurrent protection for the MOSFET. Choose the ON-resistance of the MOSFET or the value of the sense resistor in such a way that the ON-state voltage at DS does not exceed
200 mV at the maximum-load and minimum-input-voltage conditions. When using a sense resistor, TI recommends connecting a filter network between the DS pin and the sense resistor for better noise immunity.

The boost output (VIN) supplies other circuits in the system; however, they should be high-voltage tolerant. The device regulates the boost output to the programmed value only when VBAT is low, and so VIN reaches battery levels.

TPS43330A-Q1 external_drain_source_volt_sensing_SLVSC16.gif Figure 18. External Drain-Source Voltage Sensing
TPS43330A-Q1 external_current_shunt_resistor_SLVSC16.gif Figure 19. External Current Shunt Resistor

Table 2. Mode Control

SYNC
TERMINAL
COMMENTS
External clock Device in forced-continuous mode, internal PLL locks into external clock between 150 and 600 kHz.
Low or open Device enters discontinuous mode. Automatic LPM entry and exit, depending on load conditions
High Device in forced continuous mode

7.3.2 Gate-Driver Supply (VREG, EXTSUP)

The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output
(5.8 V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 to 10 µF. This pin has internal current-limit protection; do not use it to power any other circuits.

NOTE

VREG is not powered if no regulator is enabled, therefore it is not suitable to enable the regulators.

VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). If there is an expectation of VIN going to high levels, an excessive power dissipation occurs in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, powering this regulator from the EXTSUP pin, which has a connection to a supply lower than VIN but high enough to provide the gate drive, is advantageous. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically switches to EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using one of the switching regulator rails from the TPS43330A-Q1 or any other voltage available in the system to power EXTSUP. The maximum voltage for application to EXTSUP is 9 V.

TPS43330A-Q1 intgatedrvsupp_SLVSC16.gif Figure 20. Internal Gate-Driver Supply

Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as this voltage provides a large gate drive and hence better ON-resistance of the external MOSFETs.

During low-power mode, the EXTSUP functionality is unavailable. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.

7.3.3 External P-Channel Drive (GC2) and Reverse Battery Protection

The TPS43330A-Q1 includes a gate driver for an external P-channel MOSFET which can connect across the rectifier diode of the boost regulator. Such connection is useful to reduce power losses when the boost controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off the P-channel MOSFET, eliminating the diode bypass.

Another use for the gate driver is to bypass any additional protection diodes connected in series, as shown in Figure 21.

The bypass-design should be chosen with the following considerations in mind:

  • The FETs must have a current-rating to support the maximum output power at minimum voltage (before Boost gets activated, typically 1 V above the set boost-voltage). The FETs' drain-source voltage also must support the worst-case transients on VBAT, potentially causing a reverse voltage due to capacitors on the source.
  • The Zener diode protects the FET against an excessive gate-source voltage. Typically a rating of approximately 7.5 V is suitable.
  • The resistor limits the current to the FET and over the diode. Considering the deep boost mode and a high boost-output voltage, up to 9 V may be present between GC2 and VBAT, reduced by the Zener voltage. As GC2 has a drive capability of 10 mA, the current must be limited by a series resistance of about 1 kΩ (depending on VBAT(min), V(boost) and Zener voltage).

TPS43330A-Q1 reverse_battery_protection_lvsc16.gif Figure 21. Reverse Battery Protection Option 1 for Buck Boost Configuration

Figure 22 also shows a different scheme of reverse battery protection, which may require only a smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching cycle. Because the diode is not always in the series path, the system efficiency can be improved.

NOTE

Be aware that VBAT-pin is not protected against reverse polarity in this configuration.

TPS43330A-Q1 figure23b_lvsav6_v2.gif Figure 22. Reverse Battery Protection Option 2 for Buck Boost Configuration

7.3.4 Undervoltage Lockout and Overvoltage Protection

The TPS43330A-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once the device starts up, it operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device.

NOTE

If VIN drops, VREG drops as well which reduces the gate-drive voltage, whereas the digital logic is fully functional. Even if ENC is high, there is a requirement to exceed the boost-unlock voltage of typically 8.5 V once, before boost activation takes place (see Boost Controller).

A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of
5 µs (typical).

When the voltages return to the normal-operating region, the enabled switching regulators start including a new soft-start ramp for the buck regulators.

With the boost controller enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage lockout and pulls the boost-gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN falls at a rate dependent on the capacitor and load, eventually triggering VIN undervoltage. A short-falling transient at VBAT even lower than 2 V thus survives if VBAT returns above 2.5 V before VIN discharges to the undervoltage threshold.

7.3.5 Thermal Protection

The TPS43330A-Q1 protects from overheating using an internal thermal-shutdown circuit. If the die temperature exceeds the thermal-shutdown threshold of 165ºC due to excessive power dissipation (for example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off and then restart when the temperature falls by 15ºC.

7.4 Device Functional Modes

Table 3 lists the functional modes of the TPS43330A-Q1.

Table 3. Mode of Operation

ENABLE AND INHIBIT PINS DRIVER STATUS DEVICE STATUS QUIESCENT CURRENT
ENA ENB ENC SYNC BUCK CONTROLLERS BOOST CONTROLLER
Low Low Low X Shut down Disabled Shutdown Approximately 4 µA
Low High Low Low BuckB running Disabled BuckB: LPM enabled Approximately 30 µA (light loads)
High BuckB: LPM inhibited mA range
High Low Low Low BuckA running Disabled BuckA: LPM enabled Approximately 30 µA (light loads)
High BuckA: LPM inhibited mA range
High High Low Low BuckA and BuckB running Disabled BuckA and BuckB: LPM enabled Approximately 35 µA (light loads)
High BuckA and BuckB: LPM inhibited mA range
Low Low Low X Shut down Disabled Shutdown Approximately 4 µA
Low High High Low BuckB running Boost running for VIN < set boost output BuckB: LPM enabled Approximately 50 µA (no boost, light loads)
High BuckB: LPM inhibited mA range
High Low High Low BuckA running Boost running for VIN < set boost output BuckA: LPM enabled Approximately 50 µA (no boost, light loads)
High BuckA: LPM inhibited mA range
High High High Low BuckA and BuckB running Boost running for VIN < set boost output BuckA and BuckB: LPM enabled Approximately 60 µA (no boost, light loads)
High BuckA and BuckB: LPM inhibited mA range

7.4.1 Buck Controllers: Normal Mode PWM Operation

7.4.1.1 Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short-circuit to ground or a high impedance (open) at this pin sets the default switching frequency to 400 kHz. Using a resistor at RT, set another frequency according to Equation 1.

Equation 1. TPS43330A-Q1 eq20_SLVSC16.gif

For example,

600 kHz requires 40 kΩ

150 kHz requires 160 kΩ

Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz is also possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device also detects a loss of clock at this pin, and on detection of this condition, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out-of-phase.

7.4.1.2 Enable Inputs

Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins, with a threshold of 1.7 V for the high level, and with which direct connection to the battery is permissible for self-bias. The low threshold is 0.7 V. These pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device shuts down and consumes a current of less than 4 µA.

7.4.1.3 Feedback Inputs

The resistor-feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup current source as a protection feature in case the pins open up as a result of physical damage.

7.4.1.4 Soft-Start Inputs

In order to avoid large inrush currents, each buck controller has an independent programmable soft-start timer. The voltage at the SSx pin acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After start-up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes the reference for the buck controllers. Equation 2 calculates the soft-start ramp time:

Equation 2. TPS43330A-Q1 eq62_SLVSC16.gif

where

  • ISS = 50 µA (typical)
  • ∆V = 0.8 V
  • CSS is the required capacitor for ∆t, the desired soft-start time

An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be tracked through a suitable resistor-divider network.

7.4.1.5 Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing VCOMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. This process maintains the output voltage in regulation.

The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current reaches the peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of the normal frequency.

7.4.1.6 Current Sensing and Current Limit With Foldback

Clamping of the maximum value of COMPx limits the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection, which protects the high-side external MOSFET from excess current (forward-direction current limit).

Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. A clamp is on the lower end as well in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input),
50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics (see Figure 17) provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range, thus allowing DCR current-sensing using the DC resistance of the inductor for higher efficiency. Figure 23 shows DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, using the more-accurate sense resistor for current sensing is advantageous.

TPS43330A-Q1 dcr_sensing_config_SLVSC16.gif Figure 23. DCR Sensing Configuration

7.4.1.7 Slope Compensation

Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation under all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to the following:

Equation 3. TPS43330A-Q1 eq01_SLVSC16.gif

where

  • L is the buck-regulator inductor in henry
  • RS is the sense resistor in ohms
  • fsw is the buck-regulator switching frequency in hertz

7.4.1.8 Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage falls below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-drain output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant-current flow through the resistor when the buck controller is powered down.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after the same delay. Use of this delay pauses the release of the reset. Program the duration of the delay by using a suitable capacitor at the DLYAB pin according to Equation 4.

Equation 4. TPS43330A-Q1 new_EQ_SLVSC16.gif

When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently.

7.4.1.9 Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.

In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn off increases (deep-discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this switching typically occurs at 1% of the set full-load current if the choice of the inductor and sense resistor is as recommended in Slope Compensation.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until the current becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time FBx falls below the reference value. This pulsing results in a constant volt-second ton hysteretic operation with a total device-quiescent current consumption of 30 µA when a single-buck channel is active and of 35 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET.

The TPS43330A-Q1 supports the full-current load during low-power mode until the transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of full-load current if the selection of the inductor and sense resistor is as recommended. Moreover, a hysteresis always exists between the entry and exit thresholds to avoid oscillating between the two modes.

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to GND. A high (VREG) level on DIV inhibits low-power mode, unless ENC is set to low.