SLVSB16E November   2011  – December 2015 TPS43340-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Inputs
      2. 7.3.2 Linear Regulator (LREG1)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GPULL) and Reverse Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Synchronous Buck Converter Buck3
        1. 7.3.6.1 Soft Start and Foldback Functions
        2. 7.3.6.2 Current-Mode Control and Current-Limit Protection
        3. 7.3.6.3 Operation in Dropout and Undervoltage Protection
        4. 7.3.6.4 Slew Rate Control (SLEW)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.4.1.1 Setting the Operating Frequency
        2. 7.4.1.2 Feedback Inputs
        3. 7.4.1.3 Soft-Start Inputs
        4. 7.4.1.4 Current-Mode Operation
        5. 7.4.1.5 Current Sensing and Current Limit With Foldback
        6. 7.4.1.6 Slope Compensation
        7. 7.4.1.7 Reset Outputs and Filter Delays
        8. 7.4.1.8 Light-Load PFM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High- and Low-Side Power NMOS Selection for the Buck Converters
        2. 8.2.2.2 Buck1 Component Selection
        3. 8.2.2.3 Buck2 Component Selection
        4. 8.2.2.4 Buck3 Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
      1. 10.3.1 Power Dissipation of Buck1 and Buck2 (VOUT1 and VOUT2)
      2. 10.3.2 Power Dissipation of Buck Converter Buck3 (VOUT3)
        1. 10.3.2.1 High-Side Switch
        2. 10.3.2.2 Low-Side Switch
        3. 10.3.2.3 Linear Regulator (LREG1)
        4. 10.3.2.4 IC Power Consumption
    4. 10.4 Thermal Considerations
      1. 10.4.1 Phase Configuration
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS43340-Q1 multirail power supply operates with a supply voltage VIN of 4 V to 40 V for the Buck controllers and the LDO. The TPS43340-Q1 Buck converter (Buck3) operates with a supply voltage VSUP of 4 V to 10 V. For reducing power dissipation, TI strongly recommends using the output voltage of one of the buck regulators as the input supply for the LDO regulator. To use the output voltage of the buck regulator this way, the selected buck-regulator output voltage must be higher than the selected LDO-regulator output voltage. For further efficiency improvements, the part offers a pin to control an external FET that can bypass the reverse-polarity-protection diode (GPULL).

8.2 Typical Application

TPS43340-Q1 appschem_SLVSB16.gif
L1, L2, L3: DR127-8R2-R (Coiltronics)
TOP_SW3: IRF7663TRPBF (International Rectifier)
TOP_SW1, BOT_SW2: Si4946BEY-T1-E3 (Vishay)
TOP_SW2, BOT_SW2: Si4946BEY-T1-E3 (Vishay)
CBUCK1, CBUCK2, CBUCK3:AVX- TPSD107K016R0060 (AVX)
Figure 20. Application Schematic

8.2.1 Design Requirements

A few parameters must be known to begin the design process. Determination of these parameters is typically at the system level.

The following example illustrates the design process and component selection for the TPS43340-Q1. Table 1 lists the design goal parameters.

Table 1. Application Example

PARAMETER Buck1 Buck2 Buck3
Input voltage, VIN 6 V to 18 V
14 V, typical		 6 V to 18 V
14 V, typical		 4 V to 10 V
5 V, typical
Output ripple voltage ±0.2 V ±0.2 V ±0.1 V
Output voltage, VOUT 5 V ±2% 3.3 V ±2% 1.8 V ±2%
Maximum output current, IOUT 4.5 A 4.5 A 2.2 A
Minimum output current, IOUT 0.1 A 0.1 A 0.1 A
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple) ±0.3 V ±0.3 V ±0.15 V
Current-output load step, ∆IOUT 0.1 A to 4.5 A 0.1 A to 4.5 A 0.1 A to 2.2 A
Converter switching frequency, fSW 400 kHz 400 kHz 400 kHz
Junction temperature, TJ 125°C 125°C 125°C

8.2.2 Detailed Design Procedure

8.2.2.1 High- and Low-Side Power NMOS Selection for the Buck Converters

An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for these MOSFETs. The output is a totem pole, allowing full voltage drive of VREG to the gate with a peak output current of 0.6 A. The high-side MOSFET reference is the phase terminal (PHx), and the low-side MOSFET referenced is the power ground (PGNDx) terminal. For a particular application, select these MOSFETs with consideration for the following parameters rDS(on), gate charge Qg, drain-to-source breakdown voltage BVDSS, maximum dc current IDC(maximum), and thermal resistance for the package.

Power dissipation on the high-side FET (PD_HS):

Equation 7. TPS43340-Q1 eq_Pbuck1_SLVSB16.gif

First term is conduction losses.

Second term is switching losses.

Power dissipation on the low-side FET (PD_LS):

Equation 8. TPS43340-Q1 eq_Pbuck2_SLVSB16.gif

The first term in the foregoing equation refers to conduction losses, and the second term covers the switching losses in the FET body diode during the dead-time.

NOTE

rDS(on) has a positive temperature coefficient TC, which is typically 0.4%/°C.

Gate losses for high-side and low-side FETs:

Equation 9. PBuckX GATE = 2 × fsw × Qg × VREG

8.2.2.2 Buck1 Component Selection

Duty Cycle

Equation 10. TPS43340-Q1 eq_DC_B1_lvsb16.gif

Selection of Current Sensing Resistor

Equation 11. TPS43340-Q1 eq_sen_R1_lvsb16.gif

Use 10 mΩ to allow for ripple-current.

Inductor Selection L

Equation 12. TPS43340-Q1 eq_IN_Sel1_lvsb16.gif

Use 8.2 µH.

Inductor Ripple Current

Equation 13. TPS43340-Q1 eq_IN_rip1_lvsb16.gif

Output Capacitor COUT

Equation 14. TPS43340-Q1 eq_Co_1_lvsb16.gif

Use 100 µF.

Equation 15. TPS43340-Q1 eq06_SLVSB16.gif
Equation 16. TPS43340-Q1 eq07_SLVSB16.gif

Input Capacitor CIN

Equation 17. TPS43340-Q1 eq_Ci_1_lvsb16.gif

Use 10 µF, shared between Buck1 and Buck2.

High-Side MOSFET (Buck1TOPFET)

Equation 18. TPS43340-Q1 eq26_lvsa82.gif
Equation 19. TPS43340-Q1 eq_high_top_Pbuck1_lvsb16.gif

Low-Side MOSFET (Buck1LOWFET)

Equation 20. TPS43340-Q1 eq27_lvsa82.gif
Equation 21. TPS43340-Q1 eq_Low_bott_Pbuck1_SLVSB16.gif

8.2.2.3 Buck2 Component Selection

Duty Cycle

Equation 22. TPS43340-Q1 eq_DC_B2_SLVSB16.gif

Selection of Current-Sensing Resistor

Equation 23. TPS43340-Q1 eq_sen_R1_lvsb16.gif

Use 10 mΩ to allow for ripple current.

Inductor Selection L

Equation 24. TPS43340-Q1 eq_IN_Sel1_lvsb16.gif

Use 8.2 uH.

Inductor Ripple Current

Equation 25. TPS43340-Q1 eq_IN_rip2_SLVSB16.gif

Output Capacitor COUT

Equation 26. TPS43340-Q1 eq_Co_1_lvsb16.gif

Use 100 µF.

Equation 27. TPS43340-Q1 eq08_SLVSB16.gif
Equation 28. TPS43340-Q1 eq09_SLVSB16.gif

Input Capacitor CIN

Equation 29. TPS43340-Q1 eq_Ci_1_lvsb16.gif

Use 10 µF, shared between Buck1 and Buck2. For better line-transient immunity, use a larger value.

High-Side MOSFET (Buck2TOPFET)

Equation 30. TPS43340-Q1 eq26_lvsa82.gif
Equation 31. TPS43340-Q1 eq_high_top_Pbuck2_SLVSB16.gif

Low-Side MOSFET (Buck2LOWFET)

Equation 32. TPS43340-Q1 eq27_lvsa82.gif
Equation 33. TPS43340-Q1 eq_Low_bott_Pbuck2_lvsb16.gif

8.2.2.4 Buck3 Component Selection

Duty Cycle

Equation 34. TPS43340-Q1 eq_DC_B3_SLVSB16.gif

Inductor Selection LBuck3

Equation 35. TPS43340-Q1 eq_IN_Sel3_lvsb16.gif

Use 8.2 µH.

Inductor Ripple Current

Equation 36. TPS43340-Q1 eq_IN_rip3_lvsb16.gif

Output Capacitor COUT

Equation 37. TPS43340-Q1 eq_Co_3_SLVSB16.gif

Use 100 µF.

Input Capacitor CIN

Equation 38. TPS43340-Q1 eq_Ci_3_SLVSB16.gif

Use 10 µF.

Equation 39. TPS43340-Q1 eq10_SLVSB16.gif
Equation 40. TPS43340-Q1 eq11_SLVSB16.gif

Internal High-Side MOSFET (Buck3TOPFET)

Equation 41. TPS43340-Q1 eq26_lvsa82.gif
Equation 42. TPS43340-Q1 eq_high_top_Pbuck3_lvsb16.gif

Internal Low-Side MOSFET (Buck3LOWFET)

Equation 43. TPS43340-Q1 eq27_lvsa82.gif
Equation 44. TPS43340-Q1 eq_Low_bott_Pbuck3_lvsb16.gif

8.2.3 Application Curves

TPS43340-Q1 TPS43340_Loadstep_Buck1.png Figure 21. Load Step Buck 1
TPS43340-Q1 TPS43340_Loadstep_Buck3.png Figure 23. Load Step Buck 3
TPS43340-Q1 TPS43340_Loadstep_Buck2.png Figure 22. Load Step Buck 2