Refer to the PDF data sheet for device specific package drawings
The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.
The TPS51100 maintains fast transient response, only requiring 20 μF (2 × 10 μF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS51100 | HVSSOP (10) | 3.00 mm x 3.00 mm |
Changes from D Revision (May 2012) to E Revision
Changes from C Revision (June 2008) to D Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 8 | – | Signal ground. Connect to negative terminal of the output capacitor |
PGND | 4 | – | Power ground output for the VTT LDO |
S3 | 7 | I | S3 signal input |
S5 | 9 | I | S5 signal input |
VDDQSNS | 1 | I | VDDQ sense input |
VIN | 10 | I | 5-V power supply |
VLDOIN | 2 | I | Power supply for the VTT LDO and VTTREF output stage |
VTT | 3 | O | Power output for the VTT LDO |
VTTREF | 6 | O | VTT reference output. Connect to GND through 0.1-μF ceramic capacitor. |
VTTSNS | 5 | I | Voltage sense input for the VTT LDO. Connect to plus terminal of the output capacitor. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input voltage(2) | VIN, VLDOIN, VTTSNS, VDDQSNS, S3, S5 | –0.3 | 6 | V | |
PGND | –0.3 | 0.3 | |||
Output voltage(2) | VTT, VTTREF | –0.3 | 6 | V | |
TA | Operating ambient temperature | –40 | 85 | °C | |
Tstg | Storage temperature | –55 | 150 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VIN | Supply voltage | 4.75 | 5.25 | V | |
Voltage range | S3, S5 | –0.10 | 5.25 | V | |
VLDOIN, VDDQSNS, VTT, VTTSNS | –0.1 | 3.6 | |||
VTTREF | –0.1 | 1.8 | |||
PGND | –0.1 | 0.1 | |||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TPS51100 | UNIT | ||
---|---|---|---|---|
DGQ | ||||
10 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 60.3 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 63.5 | ||
RθJB | Junction-to-board thermal resistance | 51.6 | ||
ψJT | Junction-to-top characterization parameter | 1.5 | ||
ψJB | Junction-to-board characterization parameter | 22.3 | ||
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 9.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||||
IVIN | Supply current, VIN | TA = 25°C, VVIN = 5 V, no load, VS3 = VS5 = 5 V | 0.25 | 0.5 | 1 | mA | ||
IVINSTB | Standby currrent, VIN | TA = 25°C, VVIN = 5 V, no load, VS3 = 0 V, VS5 = 5 V | 25 | 50 | 80 | μA | ||
IVINSDN | Shutdown current, VIN | TA = 25°C, VVIN = 5 V, no load, VS3 = VS5 = 0 V, VVLDOIN = VVDDQSNS = 0 V | 0.3 | 1 | μA | |||
IVLDOIN | Supply current, VLDOIN | TA = 25°C, VVIN = 5 V, no load, VS3 = VS5 = 5 V | 0.7 | 1.2 | 2 | mA | ||
IVLDOINSTB | Standby currrent, VLDOIN | TA = 25°C, VVIN = 5 V, no load,VS3 = 0 V, VS5 = 5 V | 6 | 10 | μA | |||
IVLDOINSDN | Shutdown current, VLDOIN | TA = 25°C, VVIN = 5 V, no load, VS3 = VS5 = 0 V | 0.3 | 1 | μA | |||
INPUT CURRENT | ||||||||
IVDDQSNS | Input current, VDDQSNS | VVIN = 5 V, VS3 = VS5 = 5 V | 1 | 3 | 5 | μA | ||
IVTTSNS | Input current, VTTSNS | VVIN = 5 V, VS3 = VS5 = 5 V | –1 | –0.25 | 1 | μA | ||
VTT OUTPUT | ||||||||
VVTTSNS | Output voltage, VTT | VVLDOIN = VVDDQSNS = 2.5 V | 1.25 | V | ||||
VVLDOIN = VVDDQSNS = 1.8 V | 0.9 | |||||||
VVLDOIN = VVDDQSNS = 1.5 V | 0.75 | |||||||
VVTTTOL25 | Output votlage tolerance to VTTREF, VTT | VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 0 A | –20 | 20 | mV | |||
VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 1.5 A | –30 | 30 | ||||||
VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 3 A | –40 | 40 | ||||||
VVTTTOL18 | VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 0 A | –20 | 20 | |||||
VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 1 A | –30 | 30 | ||||||
VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 2 A | –40 | 40 | ||||||
VVTTTOL15 | VVLDOIN = VVDDQSNS = 1.5 V, |IVTT| = 0 A | –20 | 20 | |||||
VVLDOIN = VVDDQSNS = 1.5 V, |IVTT| = 1 A | –30 | 30 | ||||||
IVTTOCLSRC | Source current limit, VTT | ![]() |
3 | 3.8 | 6 | A | ||
VVTT = 0 V | 1.5 | 2.2 | 3 | |||||
IVTTOCLSNK | Sink current limit, VTT | ![]() |
3 | 3.6 | 6 | A | ||
VVTT = VVDDQ | 1.5 | 2.2 | 3 | |||||
IVTTLK | Leakage current, VTT | ![]() |
–1 | 0.5 | 10 | μA | ||
VS3 = 0 V, | VS5 = 5 V | |||||||
IVTTSNSLK | Leakage current, VTTSNS | ![]() |
–1 | 0.01 | 1 | μA | ||
IDSCHRG | Discharge current, VTT | TA = 25°C, VVDDQSNS = 0 V, |
VS3 = VS5 = 0 V, VVTT = 0.5 V |
10 | 17 | mA | ||
VTTREF OUTPUT | ||||||||
VVTTREF | Output voltage, VTTREF | ![]() |
V | |||||
VVTTREFTOL25 | Output voltage tolerance to VDDQSNS/2, VTTREF | VVLDOIN = VVDDQSNS = 2.5 V, IVTTREF < 10 mA | –20 | 20 | mV | |||
VVTTREFTOL18 | VVLDOIN = VVDDQSNS = 1.8 V, IVTTREF < 10 mA | –17 | 17 | |||||
VVTTREFTOL15 | VVLDOIN = VVDDQSNS = 1.5 V, IVTTREF < 10 mA | –15 | 15 | |||||
IVTTREFOCL | Source current limit, VTTREF | VVTTREF = 0 V | 10 | 20 | 30 | mA | ||
UVLO/LOGIC THRESHOLD | ||||||||
VVINUV | UVLO threshold voltage, VIN | Wake up | 3.4 | 3.7 | 4 | V | ||
Hysteresis | 0.15 | 0.25 | 0.35 | |||||
VIH | High-level input voltage | S3, S5 | 1.6 | V | ||||
VIL | Low-level input voltage | S3, S5 | 0.3 | V | ||||
VIHYST | Hysteresis voltage | S3, S5 | 0.2 | V | ||||
IILEAK | Logic input leakage current | S2, S5, | TA = 25°C | –1 | 1 | μA | ||
THERMAL SHUTDOWN | ||||||||
TSDN | Thermal shutdown threshold | Shutdown temperature | 160 | °C | ||||
Hysteresis | 10 |
The TPS51100 is a sink / source double date rate (DDR) termination regulator with VTTREF buffered reference output.
The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low-external-components systems where space is at premium, such as notebook PC applications. The TPS51100 integrates a high-performance, low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT linear regulator employs an ultimate fast-response feedback loop so that small ceramic capacitors are enough to keep tracking to the VTTREF within ±40 mV under all conditions, including fast load transient. To achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of the VTT output capacitor(s) as a separate trace from the high-current line from VTT.
The VTTREF block consists of an on-chip 1/2 divider, low-pass filter (LPF), and buffer. This regulator can source current up to 10 mA. Bypass VTTREF to GND using a 0.1-μF ceramic capacitor to ensure stable operation.
The soft-start function of the VTT is achieved via a current clamp, allowing the output capacitors to be charged with low and constant current that gives linear ramp-up of the output voltage. The current-limit threshold is changed in two stages using an internal powergood signal. When VTT is outside the powergood threshold, the current limit level is 2.2 A. When VTT rises above (VTTREF – 5%) or falls below (VTTREF + 5%), the current limit level switches to 3.8 A. The thresholds are typically VTTREF ±5% (from outside regulation to inside) and ±10% (when it falls outside). The soft-start function is completely symmetrical, and it works not only from GND to VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that the VTT output is in a high-impedance state during the S3 state (S3 = low, S5 = high), and its voltage can be up to VDDQ voltage, depending on the external condition. Note that VTT does not start under a full-load condition.
The LDO has a constant overcurrent limit (OCL) at 3.8 A. This trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of ±10% of the target voltage.
For VIN undervoltage lockout (UVLO) protection, the TPS51100 monitors VIN voltage. When the VIN voltage is lower than UVLO threshold voltage, the VTT regulator is shut off. This is a non-latch protection.
TPS51100 monitors its temperature. If the temperature exceeds the threshold value, typically 160°C, the VTT and VTTREF regulators are shut off. This is also a non-latch protection.
The S3 and S5 terminals should be connected to SLP_S3 and SLP_S5 signals, respectively. Both VTTREF and VTT are turned on at the S0 state (S3 = high, S5 = high). VTTREF is kept alive while VTT is turned off and left high-impedance in the S3 state (S3 = low, S5 = high). Both VTT and VTTREF outputs are turned off and discharged to ground through internal MOSFETs during S4/S5 state (both S3 and S5 are low).