SLVS887C April 2009 – August 2014 TPS53114
PRODUCTION DATA.
The schematic of Figure 12 shows a typical 350-kHz application schematic. The 350 kHz switching frequency is selected by connecting FSEL to the GND pin. The input voltage is 12 V and the output voltage is 1.05 V.
PARAMETERS | EXAMPLE VALUES |
---|---|
Input voltage | 12 V |
Output voltage | 1.05 V |
Output current | 4 A |
Switching frequency | 350 kHz |
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. L1 can be calculated using Equation 3.
The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current. The RMS and peak inductor current can be estimated as follows:
Note:
The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor.
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. Recommend to use ceramic output capacitor.
Where:
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and Equation 10. The capacitance for C1 should be greater than 66 μF.
Where:
Δ VOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
Tmin(off) = Minimum off time
The TPS53114 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage.
The TPS53114 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10.0 V.
The TPS53114 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1.0-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors' voltage ratings should be greater than 10 V.
The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resistors. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 or Equation 12 to calculate R1.
Where:
VFB1(ripple) = Ripple voltage at VFB1
Where:
RDS(ON) = Low side FET on-resistance
ITRIP = TRIP pin source current (≉ 10 μA)
VOCLoff = Minimum over current limit offset voltage (-20 mV)
IOCL = over current limit
Soft start timing equations are as follows:
TPS53114 power dissipation:
Where:
CiH = Input capacitor of high side MOSFET
CiL = Input capacitor of low side MOSFET
Choose package considering the Dissipation Rating table.
The application curves of Figure 13 and Figure 14 apply to both the circuits of 700 kHz Operation Application and 350-kHz Operation Application.
The schematic of Figure 18 shows a typical 700 kHz application schematic. The 700 kHz switching frequency is selected by connecting FSEL to the V5FILT pin. The input voltage is 12 V and the output voltage is 1.05 V.
PARAMETERS | EXAMPLE VALUES |
---|---|
Input voltage | 12 V |
Output voltage | 1.05 V |
Output current | 4 A |
Switching frequency | 700 kHz |
For the Detailed Design Procedure, refer to Detailed Design Procedure.
The application curves of Figure 13 and Figure 14 apply to both the circuits of 700 kHz Operation Application and 350-kHz Operation Application.