SLUS825C February   2008  – August 2014 TPS53124

PRODUCTION DATA.  

  1. 1Simplified Schematics
  2. 2Pin Configuration and Functions
  3. 3Specifications
    1. 3.1 Absolute Maximum Ratings
    2. 3.2 Handling Ratings
    3. 3.3 Recommended Operating Conditions
    4. 3.4 Thermal Information
    5. 3.5 Electrical Characteristics
    6. 3.6 Typical Characteristics
  4. 4Detailed Description
    1. 4.1 Overview
    2. 4.2 Functional Block Diagram
    3. 4.3 Feature Description
      1. 4.3.1  PWM Operation
      2. 4.3.2  Low-Side Driver
      3. 4.3.3  High-Side Driver
      4. 4.3.4  PWM Frequency and Adaptive On-Time Control
      5. 4.3.5  Soft Start
      6. 4.3.6  Output Discharge Control
      7. 4.3.7  Current Protection
      8. 4.3.8  Over/Under Voltage Protection
      9. 4.3.9  UVLO Protection
      10. 4.3.10 Thermal Shutdown
    4. 4.4 Device Functional Modes
  5. 5Application and Implementation
    1. 5.1 Application Information
    2. 5.2 Typical Application
      1. 5.2.1 Design Requirements
      2. 5.2.2 Detailed Design Procedure
        1. 5.2.2.1 Choose Inductor
        2. 5.2.2.2 Loop Compensation and External Parts Selection
        3. 5.2.2.3 Choose Input Capacitor
        4. 5.2.2.4 Choose Bootstrap Capacitor
        5. 5.2.2.5 Choose VREG5 and V5FILT Capacitor
        6. 5.2.2.6 Choose Output Voltage Set Point Resistors
        7. 5.2.2.7 Choose Over Current Set Point Resistor
        8. 5.2.2.8 Choose Soft Start Capacitor
      3. 5.2.3 Application Curves (QFN)
  6. 6Power Supply Recommendations
  7. 7Layout
    1. 7.1 Layout Guidelines
    2. 7.2 Layout Example
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Specifications

3.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input Voltage Range VIN,EN1,EN2 –0.3 26 V
VBST1,VBST2 –0.3 32
VBST1,VBST2(wrt LLx) –0.3 6
V5FILT,VFB1,VFB2,TRIP1,TRIP2,VO1,VO2, TEST1,TEST2 –0.3 6
Output Voltage Range DRVH1, DRVH2 –1 32 V
DRVH1, DRVH2 (wrt LLx) –0.3 6
LL1,LL2 –2 26
DRVL1,DRVL2,VREG5 –0.3 6
PGND1, PGND2 –0.3 0.3
Operating ambient temperature range, TA –40 85 °C
Junction Temperature Range, TJ –40 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2000 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

3.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply Input Voltage Range VIN 4.5 24 V
V5FILT 4.5 5.5
Input Voltage Range VBST1, VBST2 –0.1 30 V
VBST1, VBST2 (wrt LLx) –0.1 5.5
VFB1, VFB2, VO1, VO2 –0.1 5.5
TRIP1, TRIP2 –0.1 0.3
EN1, EN2 –0.1 24
Output Voltage Range DRVH1, DRVH2 –0.1 30 V
VBST1, VBST2 (wrt LLx) –0.1 5.5
LL1, LL2 1.8 24
DRVL1, NCDRVL2, VREG5 –0.11 5.5
PGND1, PGND2 –0.1 0.1
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 125

3.4 Thermal Information

THERMAL METRIC(1) TPS53124 TPS53124 UNIT
TSSOP (PW) RGE (QFN)
28 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 79.3 35.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.0 39.1
RθJB Junction-to-board thermal resistance 37.3 13.6
ψJT Junction-to-top characterization parameter 0.5 0.5
ψJB Junction-to-board characterization parameter 37.8 13.6
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 3.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

3.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Current
IIN VIN supply current VIN current, TA = 25°C, VREG5 tied to V5FLT, EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V, LL1 = LL2 = 0.5 V 450 800 μA
IVINSDN VIN shutdown current VIN current, TA = 25°C, no load, EN1 = EN2 = 0 V 10
VFB Voltage and Discharge Resistance
VBG Bandgap initial regulation accuracy TA = 25°C –1% 1%
VVFBTH VFB threshold voltage 　　　　　 TA = 25°C 755 765 775 mV
TA = -40°C to 85°C 752 778
IVFB VFB input current VFBx = 0.8 V, TA = 25°C –0.01 ±0.1 μA
RDISCHG VO discharge resistance ENx = 0 V, VOx = 0.5 V,TA = 25°C 40 80 Ω
VREG5 Output
VVREG5 VREG5 output voltage TA = 25°C ,5.5 V < VIN < 24 V, 0 < IVREG5 < 10 mA 4.6 5 5.2 V
VLN5 　　　 　Line regulation 5.5 V < VIN < 24 V, IVREG5 = 10 mA 20 mV
VLD5 　　　 　Load regulation 1 mA < IVREG5 < 10 mA 40
IVREG5 Output current VIN = 5.5 V, VREG5 = 4.0 V, TA = 25°C 170 mA
Output: N-Channel MOSFET Gate Drivers
RDRVH DRVH resistance Source, IDRVHx = -100 mA 5.5 11 Ω
Sink, IDRVHx = 100 mA 2.5 5
RDRVL DRVL resistance Source, IDRVLx = –100 mA 4 12 Ω
Sink, IDRVLx = 100 mA 2 4
TD Dead time DRVHx-low to DRVLx-on 20 50 80 ns
DRVLx-low to DRVHx-on 20 40 80
Internal BST Diode
VFBST Forward voltage VVREG5-VBSTx, IF = 10 mA, TA = 25°C 0.7 0.8 0.9 V
IVBSTLK VBST leakage current VBST = 29 V, LL = 24 V, TA = 25°C 0.1 1 μA
ON-Time Timer Control
TON1 CH1 ON time LL1 = 12 V, VO1 = 1.5 V 390 ns
TON2 CH2 ON time LL2 = 12 V, VO2 = 1.05 V 210
TON(min) CH2 ON time LL2 = 12 V, VO2 = 0.76 V 160
TOFF(min) CH1/CH2 min OFF time LL = 0.7 V TA = 25°C, VFB = 0.7 V 390
Soft Start
TSS Internal SS time Internal soft start VFB = 0.735 V 0.85 1.2 1.4 ms
UVLO
VUV5VFILT V5FILT UVLO threshold Wake up 3.7 4 4.3 V
Hysteresis 0.2 0.3 0.4
LOGIC Threshold
VENH ENx H-level input voltage EN 1/2 2 V
VENL ENx L-level input voltage EN 1/2 0.3
Current Sense
ITRIP TRIP source current VTRIPx = 0.1 V, TA = 25°C 8.5 10 11.5 μA
TCITRIP ITRIP temperature coefficient On the basis of 25°C 4000 ppm/°C
VOCL(off) OCP compensation offset (VTRIPx-GND - VPGNDx-LLx) voltage,VTRIPx-GND = 60 mV, TA = 25°C –10 0 10 mV
(VTRIPx-GND - VPGNDx-LLx) voltage, VTRIPx-GND = 60 mV –15 15
VR(trip) Current limit threshold setting range VTRIPx-GND voltage 30 200
Output Undervoltage and Overvoltage Protection
VOVP Output OVP trip threshold OVP detect 110% 115% 120%
TOVPDEL Output OVP prop delay 1.5 μs
VUVP Output UVP trip threshold UVP detect 65% 70% 75%
Hysteresis (recovery < 20 μs) 10%
TUVPDEL Output UVP delay 17 30 40 μs
TUVPEN Output UVP enable delay 1.2 2 2.5 ms
Thermal Shutdown
TSDN Thermal shutdown threshold Shutdown temperature(1) 150 °C
Hysteresis(1) 20
(1) Ensured by design. Not production tested.

3.6 Typical Characteristics

D001_SLUS825.gifFigure 1. VIN Supply Current vs Junction Temperature
D003_SLUS825.gifFigure 3. ITRIP Source Current vs Junction Temperature
D005_SLUS825.gifFigure 5. Switching Frequency vs Output Current
D002_SLUS825.gifFigure 2. VIN Shutdown Current vs Junction Temperature
D004_SLUS825.gifFigure 4. Switching Frequency vs Input Voltage