SLUSAF3A December   2010  – November 2016 TPS53321

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Power Good
      3. 7.3.3 Undervoltage Lockout (UVLO) Protection
      4. 7.3.4 Overcurrent Protection
      5. 7.3.5 Overvoltage Protection
      6. 7.3.6 Undervoltage Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Output Discharge
      9. 7.3.9 Master and Slave Operation and Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Modes
      2. 7.4.2 Eco-Mode™ Light-Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode (FCCM)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine the Value of R1 and R2
        2. 8.2.2.2 Choose the Inductor
        3. 8.2.2.3 Choose the Output Capacitor(s)
        4. 8.2.2.4 Choose the Input Capacitor
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPS53321 device is a high-efficiency synchronous-buck converter. The device suits low output voltage point-of-load applications with 5-A or lower output current in computing and similar digital consumer applications.

Typical Application

This design example describes a voltage-mode, 5-A synchronous buck converter with integrated MOSFETs. The device provides a fixed 1.5-V output at up to 5 A from a 3.3-V input bus.

TPS53321 v10206_lusaf3.gif Figure 13. Typical 3.3-V Input Application Circuit Diagram

Design Requirements

Table 2 lists the design specifications for this application example.

Table 2. TPS53321 Design Example Specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
Input voltage, VIN Vin 2.9 3.3 6 V
Maximum input current Vin = 3.3 V,1.5 V/5 A 2.67 A
No load input current Vin = 3.3 V,1.5 V/0 A 12.5 mA
OUTPUT CHARACTERISTICS
Output voltage, Vo 1.485 1.5 1.515 V
Output voltage regulation Line regulation 0.1%
Load regulation 1%
Output voltage ripple Vin = 3.3 V, 1.5 V/0 A to 5 A 20 mVpp
Output load current 0 5 A
Output over current 6.5 A
OUTPUT CHARACTERISTICS
Switching frequency Fixed 1.1 MHz
1.5-V full load efficiency Vin = 3.3 V, 1.5 V/5 A 85.94%
Vin = 5 V, 1.5 V/5 A 87%
Operating temperature 25 °C

Detailed Design Procedure

Determine the Value of R1 and R2

The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 13. R1 is connected between the FB pin and the output, and R2 is connected between the FB pin and GND. The recommended value for R1 is from 1 kΩ to 5 kΩ. Determine R2 using equation in Equation 1.

Equation 1. TPS53321 q_r2_lusa41.gif

Choose the Inductor

The inductance value must be determined to give the ripple current of approximately 20% to 40% of maximum output current. The inductor ripple current is determined by Equation 2.

Equation 2. TPS53321 q_ilripple_lusa41.gif

The inductor also requires low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation.

Choose the Output Capacitor(s)

The output capacitor selection is determined by output ripple and transient requirement. When operating in CC mode, the output ripple has three components calculated with Equation 3 through Equation 6.

Equation 3. TPS53321 vripple_lusa41.gif
Equation 4. TPS53321 vripplec_lusa41.gif
Equation 5. TPS53321 vrippleesr_lusa41.gif
Equation 6. TPS53321 vrippleesl_lusa41.gif

When ceramic output capacitors are used, the ESL component is usually negligible. In the case when multiple output capacitors are used, ESR and ESL must be the equivalent of ESR and ESL of all the output capacitor in parallel.

When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also varies with load current and can be expressed as shown in Equation 7.

Equation 7. TPS53321 vrippledcm_lusa41.gif

where

  • α is the DCM on-time coefficient and can be expressed in Equation 8 (typical value 1.25)
Equation 8. TPS53321 q_alpha_lusa41.gif
TPS53321 v10055_lusa41.gif Figure 14. DCM VOUT Ripple Calculation

Choose the Input Capacitor

The selection of input capacitor must be determined by the ripple current requirement. The ripple current generated by the converter must be absorbed by the input capacitors as well as the input source. The RMS ripple current from the converter can be expressed in Equation 9.

Equation 9. TPS53321 q_iinripple_lusa41.gif

where

  • D is the duty cycle and can be expressed as shown in Equation 10
Equation 10. TPS53321 q_d_lusa41.gif

To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors must be placed close to the device. The ceramic capacitor is recommended because it provides low ESR and low ESL. The input voltage ripple can be calculated as shown in Equation 11 when the total input capacitance is determined.

Equation 11. TPS53321 q_vinvripple_lusa41.gif

Compensation Design

The TPS53321 uses voltage mode control. To effectively compensate the power stage and ensure fast transient response, Type III compensation is typically used.

The control to output transfer function can be described in Equation 12.

Equation 12. TPS53321 q_gco_lusa41.gif

The output L-C filter introduces a double pole which can be calculated as shown in Equation 13.

Equation 13. TPS53321 q_fdp_lusa41.gif

The ESR zero can be calculated as shown in Equation 14.

Equation 14. TPS53321 q_fesr_lusa41.gif

Figure 15 and Figure 16 show the configuration of Type III compensation and typical pole and zero locations. Equation 16 through Equation 20 describe the compensator transfer function and poles and zeros of the Type III network.

TPS53321 v10058_lusa41.gif Figure 15. Type III Compensation Network Configuration Schematic
TPS53321 v10057_lusa41.gif Figure 16. Type III Compensation Gain Plot and Zero/Pole Placement
Equation 15. TPS53321 q_gea_lusa41.gif
Equation 16. TPS53321 q_fz1_lusa41.gif
Equation 17. TPS53321 q_fz2_lusa41.gif
Equation 18. TPS53321 q_fp1_lusa41.gif
Equation 19. TPS53321 q_fp2_lusa41.gif
Equation 20. TPS53321 q_fp3_lusa41.gif

The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a compromise between high phase margin and fast response. A phase margin higher than 45 degrees is required for stable operation.

For DCM operation, a C3 between 56 pF and 150 pF is recommended for output capacitance between 20 µF to 200 µF.

Figure 17 shows the master and slave configuration schematic for a design with a 3.3-V input.

TPS53321 v10207_lusaf3.gif Figure 17. Master and Slave Configuration Schematic

Application Curves

TPS53321 Efficiency_SLUSAF3.gif Figure 18. Efficiency
TPS53321 Line_Regulation_SLUSAF3.gif Figure 20. Line Regulation
TPS53321 Master_Slave_Synch_SLUSAF3.gif Figure 22. Master-Slave 180° Synchronization
TPS53321 Turnon_Waveform_SLUSAF3.gif Figure 24. 1.5-V Turnon Waveform
TPS53321 Load_Regulation_SLUSAF3.gif Figure 19. Load Regulation
TPS53321 Output_Ripple_SLUSAF3.gif Figure 21. 1.5-V Output Ripple
TPS53321 Output_Trans_SLUSAF3.gif Figure 23. 1.5-V Output Transient
TPS53321 Turnoff_Waveform_SLUSAF3.gif Figure 25. 1.5-V Turnoff Waveform