SLUSBG4B March   2013  – August 2021 TPS53511

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Soft Start and Pre-Biased Soft-Start Function
      4. 7.3.4 Power Good
      5. 7.3.5 Output Discharge Control
      6. 7.3.6 Current Protection
      7. 7.3.7 Overvoltage/Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
        6. 8.2.2.6 Output Voltage Setting Resistors Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Considerations
      1. 10.1.1 Thermal Information
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-D9AF800F-7FC9-4D53-9851-A990BBD71496-low.gif Figure 5-1 16-PinRGT Package(Top View)
Table 5-1 Pin Functions
PIN I/O/P DESCRIPTION
NAME NO.
EN 6 I Enable control input
GND 4 — Signal ground pin
PG 5 O Open-drain power-good output
PGND 7 P Ground returns for low-side MOSFET. Also serves as inputs of current comparators. Connect PGND and GND strongly together near the device.
8
SS 3 I/O Soft-start control. An external capacitor should be connected to GND.
SW 9 I/O Switch node connection between high-side N-channel FET and low-side N-channel FET. Also serves as inputs to current comparator.
10
11
VBST 12 I Supply input for high-side N-channel FET gate driver (boost terminal). Connect a capacitor from this pin to respective SW terminals. An internal PN diode is connected between the VREG5 and VBST pins.
VCC 15 I Supply input for 5-V internal linear regulator for the control circuitry.
VFB 1 I Converter feedback input. Connect with feedback resistor divider.
VIN 13 I Power input and connected to high side N-channel FET drain
14
VO 16 I Connect to the output of the converter. This terminal is used for on-time adjustment.
VREG5 2 O 5.5-V power supply output. A capacitor (typical 1-µF) should be connected to GND.
PowerPAD — Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND.