SLUSDP0A August 2019 – May 2021 TPS53676
PRODUCTION DATA
Interface the controller to TI smart power stage devices, as shown in Figure 7-11.
Connect the PWM pins of the controller to the PWM pins of the power stage devices. The PWM pins are three-state logic outputs of the controller. A PWM pin being logic-high commands the power stage device to turn its high-side FET on, and its low-side FET off. A PWM pin being logic-low commands the power stage device to turn its low-side FET on and its high-side FET off. TI power stage devices provide a weak drive on their PWM pins, causing them to float to a mid-level value when the controller stops driving them. During enable, or dynamic phase addition, the controller starts phases switching with a transition from tri-state to high. Similarly, during disable or dynamic phase shedding, the controller disables phases with a transition from low-to-tri-state. Float unused PWM pins on the controller.
Connect the IOUT pins of the powerstage devices to the CSP pins of the controller. Connect the VREF pin of the controller to the REFIN pins of the powerstage devices. A local bypass capacitor CVREF, is required for the controller VREF pin. Optionally, add a local VREF bypass capacitor at the powerstage devices. VREF provides common-mode voltage for the IOUT signal, which is a voltage representing the output current of each powerstage with a nominal gain of 5 mV/A. Float unused CSP pins on the controller.
Connect the TAO/FAULT pins of all powerstages within a channel to each other, and to the corresponding TSEN pin of the controller. For example, tie all TAO/FAULT pins of powerstages used on channel A together and to the controller ATSEN pin. TI recommends adding a 2200 pF capacitor to the TSEN pins at the controller to reduce temperature measurement noise. TI recommends keeping a place holder for a 1000 pF capacitor at the powerstage side. Refer to the individual powerstage datasheet for more detailed recommendations. During normal operation, the TSEN pins provide a voltage signal proportional to the temperature of the warmest powerstage device according to the equation below . During a UVLO condition, the powerstages pull the shared TAO line low to inform the controller they are not able to accept PWM input. When powerstages detect a fault condition internally, they pull the shared TAO pin high to inform the controller a fault condition has occurred. If channel B is not used, float the BTSEN pin.