SLUSDP0 Data sheet

SLUSDP0A August 2019 – May 2021 TPS53676

PRODUCTION DATA

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7.7.3 Fault behavior summary

Table 7-8 Fault detection and behavior

Fault Name	Shared / Paged / Phased	Condition	Latency	Enabled	Programmable Range	Response	Alerts ⁽¹⁾	Clearing⁽²⁾
Output Voltage / Current / Power
Pre-Bias OV Fault	Shared	VSP voltage exceeded threshold	Max 350 µs after 3.3V OK	Until initialization complete, then disabled	3.7 V fixed by design	All PWM Low, Latch-Off	VR_FAULT#	3.3 V Power Cycle
Fixed OV Fault	Paged	VSP voltage exceeded fixed threshold	1.0 µs	After initialization complete	0.6 V to 3.7 V	Ignore, Latch-Off, Hiccup PWM Pulled Low	VR_FAULT# if not ignore response	3.3 V power cycle if triggered while power conversion is disabled. Otherwise, clearable through Enable cycle, or CLEAR_FAULTS
Tracking OV Fault	Paged	VSP-VSN voltage exceeded VID + Droop + OV Offset	1.0 µs	During power conversion	Offset from current VID+Droop, +32 to +448 mV Offset	Ignore, Latch-Off, Hiccup PWM pulled low	VR_FAULT# if not ignore response	Enable cycle, or CLEAR_FAULTS
Tracking OV Warn	Paged	VSP-VSN voltage exceeded VID + Droop + OV Offset	2.0 µs	During power conversion	Offset from current VID + Droop +24 to +448 mV Offset	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Tracking UV Warn	Paged	VSP-VSN voltage below VID + Droop - UV Offset	2.0 µs	During power conversion	Offset from current VID + Droop -24 to -448 mV Offset	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Tracking UV Fault	Paged	VSP-VSN voltage below VID + Droop-UV Offset	1.0 µs	During power conversion	Offset from current VID + Droop -32 to -448 mV Offset	Ignore, Latch-Off, Hiccup PWM Tri-State	n/a	Enable cycle, or CLEAR_FAULTS
Max Turn-on time (TON_MAX)	Paged	VSP-VSN did not rise to threshold quickly enough during soft-start	500 µs	During soft-start only	0 ms to 31.75 ms	Ignore, Latch-Off, Hiccup PWM Tri-State	n/a	Enable cycle, or CLEAR_FAULTS
Vout Min/Max Warning	Paged	Vout commanded above VOUT_MAX or below VOUT_MIN	N/A	During power conversion	VOUT_MAX and VOUT_MIN	DAC Voltage clamped to limit Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Over-current Fault	Paged	Total current exceeded threshold	175 µs	During power conversion	0 to 1023 A⁽³⁾	Ignore, Latch-Off, Hiccup PWM Tri-State	VR_FAULT# configurable	Enable cycle, or CLEAR_FAULTS
Per-Phase Over-current Limit	Paged, Phased	Phase current exceeded threshold	Cycle-by-cycle	During power conversion	17 to 130 A⁽³⁾	Warning only, PWM pulses skipped to limit phase current	n/a	Enable cycle, or CLEAR_FAULTS
Current Share Warning	Paged, Phased	Phase current above or below average current for all phases by threshold	175 µs	During power conversion	5 to 20 A per phase	Warning only	n/a	Enable cycle, or CLEAR_FAULTS

(1) Any fault response which causes a shutdown event de-asserts VR_RDY. All faults have associated PMBus status bits and SMB_ALERT# response (unless masked by SMBALERT_MASK commands)

(2) Fault condition must have disappeared, otherwise fault re-triggers immediately

(3) IOUT_OC_FAULT_LIMIT[PAGE=x][PHASE=FFh] sets the per-page OC fault threshold, IOUT_OC_FAULT_LIMIT[PAGE=x][PHASE=Other] sets the per-phase OCL threshold

Table 7-9 Fault detection and behavior (continued)

Fault Name	Shared / Paged / Phased	Condition	Latency	Enabled	Programmable Range	Response	Alerts ⁽¹⁾	Clearing ⁽²⁾
Power Stage Feedback
Over-Temperature Fault	Paged	Power Stage Temperature exceeded threshold	950 µs	After initialization complete	+90 to +160 °C	Ignore, Latch-Off, Hiccup PWM Tri-State	VR_FAULT# configurable	Enable cycle, or CLEAR_FAULTS
Over-Temperature Warning	Paged	Power Stage Temperature exceeded threshold	950 µs	After initialization complete	+90 to +160 °C	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Power Stage Fault	Paged	TAO pulled high by power stage	1.0 µs	After initialization complete	TAO > 2.5 V	Ignore, Latch-Off, Hiccup PWM Tri-State	VR_FAULT# if not ignore response	Enable cycle, or CLEAR_FAULTS
Power Stage Not Ready (TAO LOW)	Paged	TAO pulled low by power stage	1.0 µs	After initialization complete	TAO < 230 mV Falling (50mV hysteresis)	Hysteresis Start-up is blocked if not yet enabled, or rail is shutdown. PWM tristated	n/a	Enable cycle, or CLEAR_FAULTS
Input Voltage / Current / Power
Input Over-Voltage Fault	Shared	VIN_CSNIN voltage exceeded threshold	950 µs	After initialization complete	0 to 19 V	Ignore, Latch-Off, Hiccup PWM Tri-State	n/a	Enable cycle, or CLEAR_FAULTS
Input Over-Voltage Warning	Shared	VIN_CSNIN voltage exceeded threshold	950 µs	After initialization complete	0 to 19 V	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Input Under-Voltage Warning	Shared	VIN_CSNIN voltage below threshold	950 µs	VIN > VIN_ON first time and either channel enabled	4.0 to 11.25 V	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Input Under-Voltage Fault	Shared	VIN_CSNIN voltage below threshold	950 µs	VIN > VIN_ON first time and either channel enabled	4.0 to 11.25 V	Ignore, Latch-Off, Hiccup PWM Tri-State	n/a	Enable cycle, or CLEAR_FAULTS
Input Over-Current Fault	Shared	CSPIN-VIN_CSNIN current below threshold	525 µs	During power conversion	4 to 128 A	Ignore, Latch-Off, Hiccup PWM Tri-State	VR_FAULT# if not ignore response	Enable cycle, or CLEAR_FAULTS
Input Over-Current Warning	Shared	CSPIN-VIN_CSNIN current below threshold	525 µs	During power conversion	4 to 128 A	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Input Over-Power Warning	Shared	Computed input power above threshold	525 µs	During power conversion	8 to 2044 W	Warning only	n/a	Enable cycle, or CLEAR_FAULTS
Self-Checking
Invalid ADDR Pinstrap	Shared	ADDR pin open, low, high, or non-convergent detection	Checked once at initialization	Checked during power-on and enable	Per detection thresholds	Latch-Off, PWM tristate	n/a	3.3 V Power Cycle
Invalid BOOT Pinstrap	Shared	BOOT pin open, low, high, or non-convergent detection	Checked once at initialization	Checked during power-on and enable	Per detection thresholds	Latch-Off, PWM tristate	n/a	3.3 V Power Cycle
PMBus Interface
PMBus Communication Error	Shared	PMBus Communication Error (See STATUS_CML)	Per PMBus communication frequency	After initialization complete	See PMBus Specification	Warning only	n/a	Enable cycle, or CLEAR_FAULTS

(1) Any fault response which causes a shutdown event de-asserts VR_RDY. All faults have associated PMBus status bits and SMB_ALERT# response (unless masked by SMBALERT_MASK commands)

(2) Fault condition must have disappeared, otherwise fault re-triggers immediately

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Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.7.3 Fault behavior summary