SLUSEZ5 December   2022 TPS53685

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Documentation Support
      1. 5.1.1 Related Documentation
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  6. 6Mechanical, Packaging, and Orderable Information
    1. 6.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS53685 is a fully AMD SVI3 compliant step-down controller with trans-inductor voltage regulator (TLVR) topology support, dual channels, built-in non-volatile memory (NVM), PMBus™ interface, and full compatible with TI NexFET™ smart power stages. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response and good current sharing, minimizing output capacitance requirements. The device also provides a novel phase interleaving strategy and dynamic phase shedding for efficiency improvements at different loads. Adjustable control of VCORE slew rate and voltage positioning work with the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS53685 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.

Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
TPS53685 QFN (40) 5.00 × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-3144E913-AA67-4953-8D81-7DE67578C454-low.gif Figure 3-1 Simplified Example Application