7.3.1 Fixed Frequency PWM Control

The TPS5401 uses an adjustable fixed-frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output is compared to the high-side power-switch current. When the power-switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. The Eco-mode control scheme is implemented with a minimum clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS5401 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.

7.3.3 Low-Dropout Operation and Bootstrap Voltage (BOOT)

The TPS5401 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage.

To improve dropout, the TPS5401 device is designed to operate at 100% duty cycle as long as the BOOT-to-PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET is turned off using an UVLO circuit, which allows the low-side diode to conduct and refresh the charge on the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor. Therefore, the effective duty cycle of the switching regulator is high.

The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode, and printed circuit board resistance. During operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT-to-PH voltage falls below 2.1 V.

Attention must be taken in maximum-duty-cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the high-side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with resistors on the EN pin.

The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26. The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output voltage within 3.5%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching.

During high-duty-cycle conditions, the inductor current ripple increases while the BOOT capacitor is being recharged, resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot capacitor being longer than the typical high-side off time, when switching occurs every cycle.

Figure 25. 3.3-V Start/Stop Voltage

Figure 26. 5-V Start/Stop Voltage

7.3.4 Error Amplifier

The TPS5401 has a transconductance amplifier as the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow-start operation, the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is 26 μA/V.

The frequency compensation components (series resistor and capacitor) are connected between the COMP pin and ground.

7.3.5 Voltage Reference

The voltage reference system produces a precise ±3.5% voltage reference over temperature by scaling the output of a temperature-stable bandgap circuit.

7.3.6 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Start with 10 kΩ for the R2 resistor and use Equation 1 to calculate R1. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator becomes more susceptible to noise, and voltage errors from the VSENSE input current become noticeable.

Equation 1.

7.3.7 Enabling and Adjusting Undervoltage Lockout

The TPS5401 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust resistors, for operation it is highly recommended to provide consistent power-up behavior. The EN pin has an internal pullup current source, I₁, of 0.9 μA that provides the default condition of the TPS5401 operating when the EN pin floats. Once the EN pin voltage exceeds the enable threshold voltage (V_ENA) of 1.25 V, an additional 2.9 μA of hysteresis, I_HYS, is added. This additional current facilitates input-voltage hysteresis. Use Equation 2 to calculate R1 which sets the external hysteresis for the input voltage. Use Equation 3 to calculate R2 which sets the input start voltage.

Figure 27. Adjustable Undervoltage Lockout (UVLO)

Equation 2.

Equation 3.

7.3.8 Slow-Start/Tracking Pin (SS/TR)

The TPS5401 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow-start time. The TPS5401 has an internal pullup current source of 2 μA that charges the external slow-start capacitor. The calculations for the slow-start time (10% to 90%) are shown in Equation 4. The voltage reference (V_ref) is 0.8 V and the slow-start current (I_SS) is 2 μA. The slow-start capacitor should remain lower than 0.47 μF and greater than 0.47 nF.

Equation 4.

At power up, the TPS5401 does not start switching until the slow-start pin is discharged to less than 40 mV to ensure a proper power up; see Figure 28.

Also, during normal operation, the TPS5401 stops switching and SS/TR must be discharged to 40 mV when the VIN UVLO is exceeded, the EN pin is pulled below 1.25 V, or a thermal shutdown event occurs.

The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage ramps linearly until clamped at 1.7 V.

Figure 28. Operation of SS/TR Pin When Starting

7.3.9 Overload Recovery Circuit

The TPS5401 has an overload recovery (OLR) circuit. The OLR circuit slow-starts the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage, using an internal pulldown of 100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed, the output slow-starts from the fault voltage to nominal output voltage.

7.3.10 Sequencing

Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open-drain output of a power-on-reset pin of another device. The sequential method is illustrated in Figure 29 using two TPS5401 devices. The power good is coupled to the EN pin on the TPS5401, which enables the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 30 shows the results of Figure 29.

Figure 29. Schematic for Sequential Start-Up Sequence

Figure 30. Sequential Start-Up Using EN and PWRGD

Figure 31. Schematic for Ratiometric Start-Up Sequence

Figure 32. Ratiometric Start-Up Using Coupled SS/TR Pins

Figure 31 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must be doubled in Equation 4. Figure 32 shows the results of Figure 31.

Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 33 to the output of the power supply that must be tracked or to another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the V_OUT2 slightly before, after, or at the same time as V_OUT1. Equation 7 is the voltage difference between V_OUT1 and V_OUT2 at the 95% of nominal output regulation.

The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (V_ssoffset) in the slow-start circuit and the offset created by the pullup current source (I_ss) and tracking resistors, the V_ssoffset and I_ss are included as variables in the equations. Figure 36 shows the result when ΔV = 0 V.

To design a ratiometric start-up in which the V_OUT2 voltage is slightly greater than the V_OUT1 voltage when V_OUT2 reaches regulation, use a negative number in Equation 5 through Equation 7 for ΔV. Equation 7 results in a positive number for applications in which V_OUT2 is slightly lower than V_OUT1 when V_OUT2 regulation is achieved. Figure 34 and Figure 35 show the start-up waveforms for negative and positive ΔV, respectively.

Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO, or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device can restart after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 8 to ensure the device can recover from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the V_ssoffset becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure 23.

Equation 5.

Equation 6.

Equation 7.

Equation 8.

Figure 34. Ratiometric Start-Up With V_OUT2 Leading V_OUT1

Figure 36. Simultaneous Start-Up

Figure 35. Ratiometric Start-Up With V_OUT1 Leading V_OUT2

7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS5401 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 9 or the curves in Figure 5 or Figure 6. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage, and minimum controllable on-time should be considered.

The minimum controllable on-time is typically 130 ns and limits the maximum operating input voltage.

The maximum switching frequency is also limited by the frequency-shift circuit. More discussion on the details of the maximum switching frequency is located as follows.

Equation 9.

7.3.12 Overcurrent Protection and Frequency Shift

The TPS5401 implements current-mode control, which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle, the switch current and COMP pin voltage are compared. When the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch-current limit.

To increase the maximum operating switching frequency at high input voltages, the TPS5401 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on the VSENSE pin.

The device implements a digital frequency shift to enable synchronizing to an external clock during normal start-up and fault conditions. Because the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still has frequency-shift protection.

During short-circuit events (particularly with high-input-voltage applications), the control loop has a finite minimum controllable on-time, and the output has a low voltage. During the switch on-time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on-time. During the switch off-time, the inductor current would normally not have enough off-time and output voltage to ramp down by the ramp-up amount. The frequency shift effectively increases the off-time, allowing the current to ramp down.

7.3.13 Selecting the Switching Frequency

The switching frequency that is selected should be the lower value of the two equations, Equation 10 and Equation 11. Use Equation 10 to calculate the maximum switching frequency limitation set by the minimum controllable on-time. Setting the switching frequency above this value causes the regulator to skip switching pulses.

Equation 11 is the maximum switching frequency limit set by the frequency-shift protection. To have adequate output short-circuit protection at high input voltages, the switching frequency should be set to be less than the f_SW(maxshift) frequency. Equation 11. To calculate the maximum switching frequency in Equation 11, account for the output voltage decrease from the nominal voltage to 0 volts and the f_DIV integer increase from 1 to 8, which corresponds to the frequency shift.

In Figure 37, the solid line illustrates a typical safe operating area regarding frequency shift and assumes an output voltage of zero volts, an inductor resistance of 0.13 Ω, FET on-resistance of 0.2 Ω, and a diode voltage drop of 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the WEBENCH design software to determine the switching frequency.

Equation 10.

where

• t_on(min) is the minimum controllable on-time
• I_L is the inductor current
• R_dc is the inductor resistance
• V_dis the diode voltage drop
• V_IN is the maximum input voltage
• V_OUT is the output voltage
• R_DS(on) is the switch-on resistance

Equation 11.

where

• ƒ_DIV is the frequency divide, which equals 1, 2, 4, or 8
• V_OUT(sc) is the output voltage during short

Figure 37. Maximum Switching Frequency vs. Input Voltage

7.3.14 How to Interface to RT/CLK Pin

The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature, connect a square wave to the RT/CLK pin as shown in Figure 38. The square-wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH signal is synchronized to the falling edge of the RT/CLK pin signal.

Figure 38. Synchronizing to a System Clock

7.3.15 Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference, the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10 kΩ and 100 kΩ connected to a voltage source that is 5.5 V or less. PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V, but with reduced current-sinking capability. PWRGD achieves full current-sinking capability as the VIN input voltage approaches 3 V.

The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, PWRGD is pulled low if the UVLO or thermal shutdown is asserted or the EN pin is pulled low.

7.3.16 Overvoltage Transient Protection

The TPS5401 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power-supply designs with low-value output capacitance. For example, when the power-supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error-amplifier output to a high voltage, thus requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power-supply output voltage can respond faster than the error-amplifier output can respond, which leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot when using a low-value output capacitor by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold, which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled, preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.

7.3.17 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power-up sequence by discharging the SS/TR pin.

7.3.18 Current-Mode Compensation Design

To simplify design efforts using the TPS5401, the typical designs for common applications are listed in Table 1. For designs using ceramic output capacitors, TI recommends proper derating of ceramic output capacitance when conducting the stability analysis because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases. Advanced users may see the Detailed Design Procedure in for detailed guidelines or use the WEBENCH tool.

7.4.1 Pulse-Skip Eco-mode Control Scheme

The TPS5401 operates in a pulse-skip Eco-mode control scheme at light load currents to improve efficiency by reducing switching and gate-drive losses. The TPS5401 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold, the device enters the Eco-mode control scheme. This current threshold is the current level corresponding to a nominal COMP voltage of 500 mV.

When in the Eco-mode control scheme, the COMP pin voltage is clamped at 500 mV, and the high-side MOSFET is inhibited. Further decreases in load current or increases in output voltage cannot drive the COMP pin below this clamp voltage level.

Because the device is not switching, the output voltage begins to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled, and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The output voltage recharges the regulated value (see Figure 39); then the peak switch current starts to decrease and eventually falls below the Eco-mode control-scheme threshold, at which time the device again enters the Eco-mode control scheme.

For Eco-mode control-scheme operation, the TPS5401 senses peak current, not average or load current, so the load current where the device enters the Eco-mode control scheme is dependent on the output inductor value. For example, the circuit in Figure 40 enters the Eco-mode control scheme at about 20 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 116 μA of input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse-skip mode, the switching transitions occur synchronously with the external clock signal.

Figure 39. Pulse-Skip Mode Operation