The desired response to a load transient is the first criteria. The output capacitor needs to supply the load with the required current when not immediately provided by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects the magnitude of voltage deviation during the transient.

In order to meet the requirements for control loop stability, this peak current mode regulator requires the addition of compensation components in the design of the error amplifier. While these compensation components provide for a stable control loop, they often also reduce the speed with which the regulator can respond to load transients. The delay in the regulator response to load changes can be two or more clock cycles before the control loop reacts to the change. During that time, the difference between the old and the new load current must be supplied (or absorbed) by the output capacitance. The output capacitor impedance must be designed to be able to supply or absorb the delta current while maintaining the output voltage within acceptable limits. Equation 22 calculates the minimum capacitance necessary to limit the voltage deviation based on a delay of two switching cycles.

Equation 22.

where

• ΔI_OUT is the change in output current
• f_SW is the switching frequency
• ΔV_OUT is the allowable change in the output voltage

For this example, the transient load response is specified as a 5% change in V_OUT for a load step of 5 A. For this example, ΔI_OUT = 5 A and ΔV_OUT = 0.05 × 1.8 = 0.09 V. Using these numbers gives a minimum capacitance of 222 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.