TPS54116-Q1 2.95-V to 6-V Input, 4-A Step-Down Converter and 1-A Source/Sink DDR Termination Regulator

Table 1. Design Parameters

8.2.2.1 Switching Frequency

The first step is to decide on a switching frequency for the regulator. The buck converter is capable of running from 100 kHz to 2.5 MHz. Typically the highest switching frequency possible is desired because it will produce the smallest solution size. A high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. Additionally in applications with EMI requirements, such as automotive, choosing a switching frequency of 2.1 MHz is desired to keep the switching noise above the medium wave band or AM band. They main trade off made with selecting a higher switching frequency is extra switching power loss, which hurt the converter’s efficiency.

The maximum switching frequency for a given application is limited by the minimum on-time of the converter and is estimated with Equation 8. For this application with the maximum minimum on-time of 125 ns at no load and 5.25 V maximum input voltage the maximum switching frequency is 2.28 MHz. A switching frequency of 2.1 MHz is selected to stay above the AM band. Equation 9 calculates R14 to be 26.8 kΩ. A standard 1% 26.7 kΩ value was chosen in the design.

Equation 8.

Equation 9.

8.2.2.2 Output Inductor Selection

To calculate the value of the output inductor, use Equation 10. K_IND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. Additionally the inductor current ripple is used as part of the PWM control system. Choosing small inductor ripple currents can degrade the transient response performance or introduce jitter in the duty cycle. In general, the inductor ripple value is at the discretion of the designer; however, K_IND is normally from 0.1 to 0.3 for the majority of applications giving a peak to peak ripple current range of 0.4 A to 1.2 A. It is recommended to always keep the peak to peak ripple current above 0.4 A because with a current mode control the inductor current ramp is used in the PWM control system.

For this design example, K_IND = 0.3 is used and the inductor value is calculated to be 0.43 μH. The next standard value 0.68 µH is selected. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 12 and Equation 13. For this design, the RMS inductor current is 4.0 A and the peak inductor current is 4.4 A. The chosen inductor is a WE 744373240068. It has a saturation current rating of 10.0 A (20% inductance loss) and a RMS current rating of 5.5 A (40 °C. temperature rise). The series resistance is 16.0 mΩ typical.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the steady-state peak inductor current. Additionally if a hard short on the output occurs in a fault condition the peak inductor current can exceed the current limit and may reach up to 10 A. The peak current limit in this scenario is only limited by the minimum on-time of the TPS54116-Q1 and the parasitic DC voltage drops in the circuit. The peak current during a hard short will vary with the switching frequency and only exceeds the current limit when using the TPS54116-Q1 with higher switching frequencies like 2.1 MHz. To protect the inductor in a hard output short the inductor should be rated for this current.

Equation 10.

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Equation 11.

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Equation 12.

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Equation 13.

8.2.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criteria and is often the most stringent. The output capacitor needs to supply the increased load current until the regulator responds to the load step. The regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. At higher switching frequencies the fastest response time is about 4 µs. Equation 14 shows the minimum output capacitance necessary, where ΔI_OUT is the change in output current, tresponse is the regulators response time and ΔV_OUT is the allowable change in the output voltage. The minimum of 2/fsw or 4 µs should be used for the response time in the output capacitance calculation. It is important to realize the response to a transient load also depends on the loop compensation and slew rate of the transient load. This calculation assumes the loop compensation is designed for the output filter with the equations later on in this procedure.

For this example, the transient load response is specified as a 4% change in VOUT for a load step of 2 A. Therefore, ΔI_OUT is 2 A and ΔV_OUT = 0.04 × 1.5 = 60 mV. Using these numbers with a 4 µs response time gives a minimum capacitance of 133 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be considered for load step response.

Equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 7.5 mV. Under this requirement, Equation 15 yields 6.3 µF.

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Equation 14.

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Equation 15.

Where:

• ΔI_OUT is the change in output current
• fsw is the regulators switching frequency
• ΔV_OUT is the allowable change in the output voltage

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Equation 16 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification and this shows the ESR should be less than 10 mΩ. In this case ceramic capacitors will be used and the combined ESR of the ceramic capacitors in parallel is much less than 10 mΩ. Capacitors also generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 17 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 17 yields 220 mA. Ceramic capacitors used in this design will have a ripple current rating much higher than 220 mA.

Equation 16.

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Equation 17.

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this application example, three 47 μF 10 V 1210 X7R ceramic capacitors each with 8 mΩ of ESR at the fsw are used. The estimated capacitance after derating shown on the capcaitor manufacturer's website with 1.5 V DC bias is 51.4 µF each. With 3 parallel capacitors the total output capacitance is 154 µF and the ESR is 2.7 mΩ.

8.2.2.4 Input Capacitor

The TPS54116-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF of effective capacitance placed across the PVIN and PGND pins and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum RMS input current of the TPS54116-Q1. The RMS input current can be calculated using Equation 18. An input decoupling capacitor of 1 µF must also be placed at the AVIN pin to ensure a stable input voltage to the internal control circuits.

For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 47 µF 1210 X7R, one 10 µF 0603 X7R and one 0.1 μF 0603 X7R 10 V capacitors in parallel have been selected for the PVIN to PGND pins. Additionally one 1 µF 0603 X5R 10 V capacitor is selected for the AVIN pin. The 0.1 µF at the PVIN pin is used to better bypass the higher frequency content when the high-side MOSFET switches on and off. Based on the capacitor manufacturer's website, the total input capacitance derates to 34 µF at the nominal input voltage of 5 V. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 19. Using the design example values, Ioutmax = 4 A, Cin = 34 μF, f_SW = 2.1 MHz, yields an input voltage ripple of 14 mV and a rms input ripple current of 1.9 A.

Equation 18.

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Equation 19.

8.2.2.5 Soft Start Capacitor

The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54116-Q1 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The soft-start capacitor value can be calculated using Equation 20. For the example circuit, the soft-start time is not too critical since the output capacitor value of 3 x 47 µF does not require much current to charge to 1.5 V. With the higher switching frequency used in this example a faster start-up time improves the start up behavior. Near the beginning of the start up time when the output voltage is low the minimum on-time of the converter is too large to regulate the output causing additional ripple on the output. A faster start-up time will reduce the time the converter spends in this region. The example circuit is designed for a soft-start time of 0.6 ms which requires a 3300 pF capacitor.

Equation 20.

8.2.2.6 Undervoltage Lock Out Set Point

The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the ENSW and ENLDO pin of the TPS54116. Each pin can have its own resistor divider if different thresholds are needed for the VTT LDO and the buck converter. If only one threshold is needed only one resistor divider is needed and the pins can be connected in parallel. If connected in parallel the pull up current and hysteresis current should be increased to 3.4 µA and 5.1 µA respectively as shown in the electrical specifications. The UVLO has two thresholds, one for power-up when the input voltage is rising, and one for power-down or brown outs when the input voltage is falling.

For the example design, the supply should turn on and start switching once the input voltage increases above 2.9 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 2.6 V (UVLO stop). The EN pins are also connected in parallel so the higher pull up current and hysteresis current is used. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. A 45.3 kΩ between PVIN and the EN pins (R1) and a 30.1 kΩ between the EN pins and ground (R2) are used producing a start voltage of 2.85 V and stop voltage of 2.47 V. The 2.47 V stop voltage is below the 2.65 V AVIN UVLO so with this application example the TPS54116-Q1 will turn off due to the AVIN UVLO.

8.2.2.7 Bootstrap Capacitor

A 0.1 μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating.

8.2.2.8 Power Good Pullup

A 100 kΩ resistor is used to pull up the power good signal to VIN when FB conditions are met.

8.2.2.9 ILIM Resistor

The recommended peak current limit is calculated with Equation 21 using ILpeak from Equation 13. This calculation includes 10% margin for load transients and an additional 1.5 A for the tolerance of the peak current limit. In this application a 100 kΩ resistor is placed from ILIM to AGND to set the peak current limit to its maximum value. For applications requiring a different peak current limit Equation 7 is used to calculate the ILIM resistor.

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Equation 21.

8.2.2.10 Output Voltage and Feedback Resistors Selection

For the example design, 10.0 kΩ was selected for R7. Using Equation 22, R5 is calculated as 15.0 kΩ which is a standard 1% resistor.

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Equation 22.

8.2.2.11 Compensation

There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low ESR output capacitors. Use the WEBENCH software for more accurate loop compensation. These tools include a more comprehensive model of the control loop.

To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 23 and Equation 24. For Cout, use a derated value of 154 μF. Use equations Equation 25 and Equation 26, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 2.8 kHz and fzmod is 388 kHz. Equation 25 is the geometric mean of the modulator pole and the esr zero and Equation 26 is the mean of modulator pole and one half the switching frequency or 250 kHz, whichever is larger. For the 2.1 MHz switching frequency application 250 kHz is used so Equation 25 yields 33 kHz and Equation 26 gives 52 kHz. Use the lower value of Equation 25 or Equation 26 for an initial crossover frequency. Next, the compensation components are calculated. A resistor-in-series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 23.

Equation 24.

Equation 25.

Equation 26.

To determine the compensation resistor, R6, use Equation 27. Assume the power stage transconductance, gmps, is 16 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 1.5 V, 0.6 V and 260 μA/V, respectively. R6 is calculated to be 19 kΩ and the closest standard value 19.1 kΩ. Use Equation 28 to set the compensation zero to the modulator pole frequency. Equation 28 yields 3020 pF for compensating capacitor C6 and the closest standard value is 3300 pF.

Equation 27.

Equation 28.

A compensation pole is implemented using an additional capacitor C7 in parallel with the series combination of R6 and C6. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal. Use the larger value of Equation 29 and Equation 30 to calculate the C7, to set the compensation pole. C7 is calculated to 21 pF or 8 pF and the closest standard value is 22 pF.

Equation 29.

Equation 30.

Type III compensation is used by adding the feed forward capacitor (C17) in parallel with the upper feedback resistor. This increases the crossover and adds phase boost above what is normally possible from Type II compensation. It places an additional zero/pole pair. This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well. The zero is placed at the intended crossover frequency by calculating the value of C17 with Equation 31. The calculated value is 216 pF and the closest standard value is 220 pF.

Equation 31.

The initial compensation based on these calculations is R6 = 19.1 kΩ, C6 = 3300 pF, C7 = 22 pF and C17 = 220 pF. These values yield a stable design but after testing the real circuit these values were changed to optimize performance. The final values used in the schematic are R6 = 20.5 kΩ, C6 = 1800 pF, C7 = 180 pF and C17 = 180 pF.

8.2.2.12 LDOIN Capacitor

Depending on the trace impedance between the LDOIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the LDOIN input capacitor. Use a 10-µF (or greater) and X5R grade (or better) ceramic capacitor to supply this transient charge.

8.2.2.13 VTTREF Capacitor

Add a ceramic capacitor, with a value 0.22 µF and X5R grade (or better), placed close to the VTTREF terminal for stable operation.

8.2.2.14 VTT Capacitor

For stable operation, two 10-µF (or greater) and X5R (or better) grade ceramic capacitor(s) need to be attached close to the VTT terminal. This capacitor is recommended to minimize any additional equivalent series resistance (ESR) and/or equivalent series inductance (ESL) of ground trace between the PGND terminal and the VTT capacitor(s).