SLUS973A October   2009  – November 2016 TPS54290 , TPS54291 , TPS54292

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Voltage Reference
      2. 8.3.2  Oscillator
      3. 8.3.3  Input UVLO and Start-Up
      4. 8.3.4  Enable and Timed Turnon of the Outputs
      5. 8.3.5  Soft Start
      6. 8.3.6  Output Voltage Regulation
      7. 8.3.7  Inductor Selection
      8. 8.3.8  Maximum Output Capacitance
      9. 8.3.9  Feedback Loop Compensation
      10. 8.3.10 Bootstrap for N-Channel MOSFET
      11. 8.3.11 Output Overload Protection
      12. 8.3.12 Operating Near Maximum Duty Cycle
      13. 8.3.13 Dual-Supply Operation
      14. 8.3.14 Bypassing and Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 Standby Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS54291 Design Example
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Duty Cycle Estimation
          2. 9.2.1.2.2  Inductor Selection
          3. 9.2.1.2.3  Output Capacitor Selection
          4. 9.2.1.2.4  Input Capacitor Selection
          5. 9.2.1.2.5  Feedback
          6. 9.2.1.2.6  Compensation Components
          7. 9.2.1.2.7  Compensation Gain Setting Resistor
          8. 9.2.1.2.8  Compensation Integrator Capacitor
          9. 9.2.1.2.9  Bootstrap Capacitor
          10. 9.2.1.2.10 Power Dissipation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPS54290 Cascaded Design Example
        1. 9.2.2.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PowerPAD™ Package
    2. 11.2 Layout Examples
    3. 11.3 Overtemperature Protection and Junction Temperature Rise
    4. 11.4 Power Derating
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
PVDD1, PVDD2, EN1, EN2 –0.3 20 V
SW1, SW2 –1 20 V
BOOT1, BOOT2 –0.3 SW + 7 V
SW1, SW2 transient (< 50 ns) –3 20 V
BP 7 V
FB1, FB2 –0.3 3 V
Operating junction temperature, TJ –40 145 °C
Storage temperature, Tstg –55 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Input voltage 4.5 18 V
TJ Junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS54290
TPS54291
TPS54292		 UNIT
PWP (HTSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 39.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.7 °C/W
RθJB Junction-to-board thermal resistance 22.3 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 22.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

TJ = –40°C to 125°C, PVDD1 and PVDD2 = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
PVDD1, PVDD2 Input voltage range 4.5 18 V
IDDSDN Shutdown current EN1 = EN2 = PVDD2 (4.5 V to 18 V) 80 160 µA
IDDQ Quiescent, non-switching FB1 = FB2 = 1 V, outputs off 1.65 3 mA
IDDSW Quiescent, while switching FB1 = FB2 = 0.75 V, measured at BP 10 mA
UVLO Minimum turnon voltage PVDD2 only 3.8 4.1 4.4 V
UVLOHYS Hysteresis 460 600 mV
tstart(1)(2) Time from start-up to soft start begin CBP = 10 µF, EN1 and EN2 go low simultaneously 1.5 ms
ENABLE (ACTIVE LOW)
VENx Enable threshold voltage 0.9 1.2 1.5 V
Hysteresis 70 mV
IENx Enable pullup current 10 µA
tENx(1) Time from enable to soft start begin Other enable pin = GND 10 µs
BP REGULATOR
BP Regulator voltage 8 V ≤ VPVDD2 ≤ 18 V 5 5.2 5.6 V
BPLDO Dropout voltage VPVDD2 = 4.5 V 400 mV
IBPS Regulator short current 4.5 V ≤ VPVDD2 ≤ 18 V 25 mA
OSCILLATOR
fSW Oscillator frequency TPS54290 260 300 360 kHz
TPS54291 520 600 720
TPS54292 1040 1200 1440 kHz
tDEAD(1) Clock dead time 140 ns
gMTRANSCONDUCTANCE AMPLIFIER AND VOLTAGE REFERENCE (APPLIES TO BOTH CHANNELS)
VFB Feedback input voltage 0°C < TJ < 85°C 792 800 808 mV
–40ºC < TJ < 125°C 786 800 812 mV
IFB Feedback Input bias current VFB = 0.8 V 5 50 nA
gM(1) Transconductance 200 325 450 µS
ISOURCE Error amplifier source current capability VFB1 = VFB2 = 0.7 V, VCOMP = 0 V 15 30 40 µA
ISINK Error amplifier sink current capability VFB1 = VFB2 = 0.9 V, VCOMP = 2 V 15 30 40 µA
SOFT START (APPLIES TO BOTH CHANNELS)
tSS Soft-start time TPS54290, 0 V ≤ VFB ≤ 0.8 V 4 5.2 6 ms
TPS54291 2 2.6 3
TPS54292 1 1.3 1.6
OVERCURRENT PROTECTION
ICL1 Current limit CH1 1.8 2.2 2.6 A
ICL2 Current limit CH2 3.2 3.8 4.6 A
THICCUP(1) Hiccup timeout TPS54290 30 ms
TPS54291 16
TPS54292 8
tONOC(1) Minimum overcurrent pulse 150 200 ns
BOOTSTRAP (APPLIED TO BOTH CHANNELS)
RBOOT Bootstrap switch resistance R(BP to BOOT), I external = 10 mA 33 Ω
PGOOD
VUV Feedback voltage limit for PGOOD 660 730 mV
VPG-HYST(1) PGOOD hysteresis voltage on FB 40 mV
OUTPUT STAGE (APPLIED TO BOTH CHANNELS)
RDS(on1)(HS)(1) On-resistance of high-side FET and bondwire on CH1 170 265 mΩ
RDS(on2)(HS)(1) On-resistance of high-side FET and bondwire on CH2 120 190 mΩ
RDS(on1)(LS)(1) On-resistance of low-side FET and bondwire on CH1 120 190 mΩ
RDS(on2)(LS)(1) On-resistance of low-side FET and bondwire on CH2 90 150 mΩ
tON_MIN (1) Minimum controllable pulse width 150 ns
Minimum duty cycle VFB = 0.9 V 0%
tDEAD(1) Output driver dead time HDRV off to LDRV on 20 ns
LDRV off to HDRV on 20 ns
DMAX Maximum duty cycle TPS54290 90% 96%
TPS54291 85% 91%
TPS54292 78% 82%
THERMAL SHUTDOWN
TSD(1) Shutdown temperature 145 °C
TSD_HYS(1) Hysteresis 20 °C
(1) Specified by design. Not tested in production.
(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value (see Input UVLO and Start-Up)

7.6 Typical Characteristics

TPS54290 TPS54291 TPS54292 iddq_v_tj_lus973.gif Figure 1. Quiescent Current vs Temperature
TPS54290 TPS54291 TPS54292 vuvlo_v_tj_lus973.gif Figure 3. UVLO Turnon and Turnoff Thresholds
vs Temperature
TPS54290 TPS54291 TPS54292 tss_v_tj_lus973.gif Figure 5. Soft-Start Time vs Temperature
TPS54290 TPS54291 TPS54292 vfb_v_tj_lus973.gif Figure 7. Feedback Voltage vs Temperature
TPS54290 TPS54291 TPS54292 vbp_v_tj_lus973.gif Figure 9. BP Voltage vs Temperature
TPS54290 TPS54291 TPS54292 isd_v_tj_lus973.gif Figure 2. Shutdown Current vs Temperature
TPS54290 TPS54291 TPS54292 ven_v_tj_lus973.gif Figure 4. ENx Turnon and Turnoff Threshold
vs Temperature
TPS54290 TPS54291 TPS54292 fsw_v_tj_lus973.gif Figure 6. Oscillator Frequency vs Temperature
TPS54290 TPS54291 TPS54292 ilimx_v_tj_lus973.gif Figure 8. Current Limit vs Temperature
TPS54290 TPS54291 TPS54292 iswoff_v_tj_lus973.gif Figure 10. SW Node Leakage Current
vs Temperature