SLVSBZ1A September   2013  – November 2015 TPS54340-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 RT/CLK Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode™
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switchign Frequency
      11. 7.3.11 Synchronization to RT/CLK Pin
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small-Signal Model for Loop Response
      15. 7.3.15 Simple Small-Signal Model for Peak-Current-Mode Control
      16. 7.3.16 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 3.5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting the Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection (LO)
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Catch Diode
          5. 8.2.1.2.5  Input Capacitor
          6. 8.2.1.2.6  Bootstrap-Capacitor Selection
          7. 8.2.1.2.7  Undervoltage Lockout Set Point
          8. 8.2.1.2.8  Output Voltage and Feedback Resistors Selection
          9. 8.2.1.2.9  Compensation
          10. 8.2.1.2.10 Power Dissipation Estimate
          11. 8.2.1.2.11 Discontinuous Conduction Mode and Eco-mode™ Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power Supply
      3. 8.2.3 Split-Rail Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DDA Package
8-Pin HSOP
Top View
TPS54340-Q1 po_lvsBB4.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 O A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high-side MOSFET, the output switches off until the capacitor is refreshed.
COMP 6 O Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this pin.
EN 3 I Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
FB 5 I Inverting input of the transconductance (gm) error amplifier.
GND 7 — Ground
RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is reenabled and the operating mode returns to resistor frequency programming.
SW 8 I The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad 9 — GND pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation.
VIN 2 I Input supply voltage with 4.5-V to 42-V operating range.