SLVSBZ1A September   2013  – November 2015 TPS54340-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 RT/CLK Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode™
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switchign Frequency
      11. 7.3.11 Synchronization to RT/CLK Pin
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small-Signal Model for Loop Response
      15. 7.3.15 Simple Small-Signal Model for Peak-Current-Mode Control
      16. 7.3.16 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 3.5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting the Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection (LO)
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Catch Diode
          5. 8.2.1.2.5  Input Capacitor
          6. 8.2.1.2.6  Bootstrap-Capacitor Selection
          7. 8.2.1.2.7  Undervoltage Lockout Set Point
          8. 8.2.1.2.8  Output Voltage and Feedback Resistors Selection
          9. 8.2.1.2.9  Compensation
          10. 8.2.1.2.10 Power Dissipation Estimate
          11. 8.2.1.2.11 Discontinuous Conduction Mode and Eco-mode™ Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power Supply
      3. 8.2.3 Split-Rail Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 45 V
EN –0.3 8.4
BOOT 53
FB –0.3 3
COMP –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-SW 8 V
SW –0.6 45
SW, 10-ns Transient –2 45
Operating junction temperature –40 150 °C
Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply input voltage 4.5 42 V
VO Output voltage 0.8 58.8 V
IO Output current 0 3.5 A
TJ Junction Temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54340-Q1 UNIT
DDA (HSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance (standard board) 42 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 45.8 °C/W
RθJB Junction-to-board thermal resistance 23.4 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 23.4 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 3.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 4.5 42 V
Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V
Internal undervoltage lockout threshold hysteresis 325 mV
Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V 2.25 4.5 μA
Operating: nonswitching supply current FB = 0.9 V, TA = 25°C 146 175
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
Input current Enable threshold 50 mV –4.6 μA
Enable threshold –50 mV –0.58 –1.2 -1.8
Hysteresis current –2.2 –3.4 -4.5 μA
Enable to COMP active VIN = 12 V , TA = 25°C 540 µs
INTERNAL SOFT-START TIME
Soft-Start Time fSW = 500 kHz, 10% to 90% 2.1 ms
Soft-Start Time fSW = 2.5 MHz, 10% to 90% 0.42 ms
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μS
Error amplifier transconductance (gM) during soft-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μS
Error amplifier DC gain VFB = 0.8 V 10,000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source and sink V(COMP) = 1 V, 100-mV overdrive ±30 μA
COMP to SW current transconductance 12 A/V
CURRENT LIMIT
Current limit threshold All VIN and temperatures, Open Loop(1) 4.5 5.5 6.8 A
All temperatures, VIN = 12 V, Open Loop(1) 4.5 5.5 6.25
VIN = 12 V, TA = 25°C, Open Loop(1) 5.2 5.5 5.85
Current limit threshold delay 60 ns
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.

6.6 RT/CLK Timing Requirements

MIN NOM MAX UNIT
Minimum CLK input pulse width 15 ns

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 100 2500 kHz
ƒSW Switching frequency RT = 200 kΩ 450 500 550 kHz
Switching frequency range using CLK mode 160 2300 kHz
RT/CLK falling edge to SW rising edge delay Measured at 500 kHz with RT resistor in series 55 ns
PLL lock in time Measured at 500 kHz 78 μs

6.8 Typical Characteristics

TPS54340-Q1 G001_SLVSBB4.png
Figure 1. ON Resistance vs Junction Temperature
TPS54340-Q1 G003_SLVSBB4.png
Figure 3. Switch Current Limit vs Junction Temperature
TPS54340-Q1 G005_SLVSBB4.png
Figure 5. Switching Frequency vs Junction Temperature
TPS54340-Q1 G007_SLVSBB4.png
Figure 7. Switching Frequency vs RT/CLK Resistance
High-Frequency Range
TPS54340-Q1 G009_SLVSBB4.png
Figure 9. EA Transconductance During Soft Start vs Junction Temperature
TPS54340-Q1 G011_SLVSBB4.gif
Figure 11. EN Pin Current vs Junction Temperature
TPS54340-Q1 G0112a_SLVSBB4.png
Figure 13. EN Pin Current Hysteresis vs
Junction Temperature
TPS54340-Q1 G014_SLVSBB4.png
Figure 15. Shutdown Supply Current vs
Junction Temperature
TPS54340-Q1 G016_SLVSBB4.png
Figure 17. VIN Supply Current vs Junction Temperature
TPS54340-Q1 G018_SLVSBB4.png
Figure 19. BOOT-SW UVLO vs Junction Temperature
TPS54340-Q1 G021_SLVSBB4.gif
Figure 21. Soft-Start Time vs Switching Frequency
TPS54340-Q1 G002_SLVSBB4.png
Figure 2. Voltage Reference vs Junction Temperature
TPS54340-Q1 G004_slvsBK0.gif
Figure 4. Switch Current Limit vs Input Voltage
TPS54340-Q1 G006_SLVSBB4.png
Figure 6. Switching Frequency vs RT/CLK Resistance
Low-Frequency Range
TPS54340-Q1 G008_SLVSBB4.png
Figure 8. EA Transconductance vs Junction Temperature
TPS54340-Q1 G010_SLVSBB4.png
Figure 10. EN Pin Voltage vs Junction Temperature
TPS54340-Q1 G012_SLVSBB4.gif
Figure 12. EN Pin Current vs Junction Temperature
TPS54340-Q1 G013_SLVSBB4.png
Figure 14. Switching Frequency vs FB
TPS54340-Q1 G016_slvsBK0.gif
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
TPS54340-Q1 G018_slvsBK0.gif
Figure 18. VIN Supply Current vs Input Voltage
TPS54340-Q1 G019_SLVSBB4.png
Figure 20. Input Voltage UVLO vs Junction Temperature
TPS54340-Q1 C026_SLVSBO1.png
Figure 22. 5-V Start and Stop Voltage
(see Low Dropout Operation and Bootstrap Voltage (BOOT))