SLVSCC4B April   2014  – January 2017 TPS54361-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjust Undervoltage Lockout
      8. 7.3.8  Soft-Start/Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      11. 7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Power Good (PWRGD Pin)
      14. 7.3.14 Overvoltage Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small Signal Model for Loop Response
      17. 7.3.17 Simple Small Signal Model for Peak Current Mode Control
      18. 7.3.18 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with V(VIN) = < 4.5 V (Minimum V(VIN))
      2. 7.4.2 Operation with EN Control
      3. 7.4.3 Alternate Power Supply Topologies
        1. 7.4.3.1 Inverting Power Supply
        2. 7.4.3.2 Split Rail Power Supply
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection (LO)
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Catch Diode
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Slow-Start Capacitor
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  Undervoltage Lockout Set Point
        10. 8.2.2.10 Output Voltage and Feedback Resistors Selection
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation Estimate
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Custom Design with WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. See Figure 68 for a PCB layout example.

  • To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
  • Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
  • The GND pin should be tied directly to the thermal pad under the IC. The thermal pad should be connected to internal PCB ground planes using multiple vias directly under the IC.
  • For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
  • The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace.
  • The additional external components can be placed approximately as shown.
  • It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

Boxing in the components in the design of Figure 48 the estimated printed circuit board surface area is 1.025 in2 (661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can be done by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent.

10.1.1 Power Dissipation Estimate

The following formulas show how to estimate the TPS54361-Q1 power dissipation under continuous conduction mode (CCM) operation. These equations must not be used if the device is operating in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (PCON), switching loss E, gate drive loss (Pg) and supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.

  1. Conduction loss
    2. Equation 56. TPS54361-Q1 eq_56_slvscc4.gif

    where

    • IO is the output current (A)
    • rDS(on) is the on-resistance of the high-side MOSFET (Ω)
    • VO is the output voltage (V)
    • V(VIN) is the input voltage (V)
  2. Switching loss:
    3. Equation 57. E = VI × ƒS × IO × tr = 12 V × 600 kHz × 3.5 A × 4.9 ns = 0.123 A

    where

    • E is the switching loss
    • ƒS is the switching frequency (Hz)
    • tr is the SW pin voltage rise time and can be estimated by trise = V(VIN) × 0.16 ns/V + 3 ns
  3. Gate charge loss:
    4. Equation 58. PG = V(VIN) × Qg × ƒS = 12 V × 3 nC × 600 kHz = 0.022 W

    where

    • Qg is the total gate charge of the internal MOSFET
  4. Quiescent current loss:
    5. Equation 59. PQ = V(VIN) × IQ = 12 V × 152 µA = 0.0018 W

    where

    • IQ is the operating nonswitching supply current

Therefore,

Equation 60. Ptot = PCON + E + PG + PQ = 0.45 W + 0.123 W + 0.022 W + 0.0018 W = 0.597 W

For given TA:

Equation 61. TJ = TA + Rth × Ptot

where

  • TA is the ambient temperature (°C)
  • TJ is the junction temperature (°C)
  • Ptot is the total device power dissipation (W)
  • Rth is the thermal resistance of the package (°C/W)

For given TJmax = 150°C:

Equation 62. TAmax = TJmax – Rth × Ptot

where

  • TJmax is maximum junction temperature (°C)
  • TAmax is maximum ambient temperature (°C)

Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode, and PCB trace resistance impacting the overall efficiency of the regulator.

10.2 Layout Example

TPS54361-Q1 layout_slvscc4.gif Figure 68. PCB Layout Example