7.3.1 Fixed-Frequency PWM Control

The TPS54361 device uses fixed-frequency peak current-mode control with adjustable switching frequency. The output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output at the COMP pin controls the high-side power-switch current. When the high-side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements current-limiting by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a minimum voltage clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS54361 device adds a compensating ramp to the MOSFET switch-current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.

7.3.3 Pulse-Skip Eco-Mode

The TPS54361 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. The device enters Eco-mode if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold. The pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of 600 mV.

When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited. Because the device is not switching, the output voltage begins to decay. The voltage control-loop responds to the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54361 device senses and controls the peak switch current and not the average load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor value. As the load current approaches zero, the device enters a pulse-skip mode during which it draws only a 152-μA input quiescent current. The circuit in Figure 46 enters Eco-mode at about a 25-mA output current and with no external load has an average input current of 260 µA.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54361 device provides an integrated bootstrap voltage-regulator. A small capacitor between the BOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R-grade dielectric with a voltage rating of 10 V or higher is recommended for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54361 device operates at a 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high output voltages, the small low-side MOSFET disables at 24-V output and re-enables when the output reaches 21.5 V.

Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode voltage and the printed circuit board (PCB) resistance.

The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within 1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where switching stops.

During high duty-cycle (low-dropout) conditions, inductor current ripple increases when the BOOT capacitor is being recharged which results in an increase in output voltage ripple. Increased ripple occurs when the off time required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle PWM control.

At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 1 calculates the minimum input voltage for this condition.

7.3.5 Error Amplifier

The TPS54361 voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifier compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 350 μS during normal operation. During soft-start operation, the transconductance is reduced to 78 μS and the error amplifier is referenced to the internal soft-start voltage.

The frequency compensation components (capacitor, series resistor, and capacitor) are connected between the error amplifier output COMP pin and GND pin.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor divider from the output node to the FB pin. Divider resistors with a 1%-tolerance or better are recommended. Select the low-side resistor R_LS for the desired divider current and use Equation 2 to calculate R_HS. To improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator is more susceptible to noise and voltage errors from the FB input current may become noticeable.

Equation 2.

7.3.7 Enable and Adjust Undervoltage Lockout

The TPS54361 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the enable threshold of 1.2 V. The TPS54361 device disables when the VIN pin voltage falls below 4 V or when the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I₁, of 1.2 μA that enables operation of the TPS54361 device when the EN pin floats.

If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 26 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis current, I_HYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3-μA I_HYS current is removed. This additional current facilitates the adjustable input-voltage UVLO hysteresis. Use Equation 3 to calculate R_UVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R_UVLO2 for the desired VIN start voltage.

In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high input voltages (that is, from 40 V to 60 V), the EN pin experiences a voltage greater than the absolute maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN resistors, the EN pin is clamped internally with a 5.8-V Zener diode that sinks up to 150 μA.

Equation 3.

Equation 4.

Figure 26. Adjustable Undervoltage Lockout (UVLO)

Figure 27. Internal EN Pin Clamp

7.3.8 Soft-Start/Tracking Pin (SS/TR)

The TPS54361 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a soft-start time. The TPS54361 has an internal pullup current source of 1.7 μA that charges the external soft-start capacitor. The calculations for the soft-start time (10% to 90%) are shown in Equation 5. The voltage reference (V_REF) is 0.8 V and the soft-start current (I_SS) is 1.7 μA. The soft-start capacitor must remain lower than 0.47 μF and greater than 0.47 nF.

Equation 5.

At power up, the TPS54361 device does not start switching until the soft-start pin is discharged to less than 54 mV to ensure a proper power up, see Figure 28.

Also, during normal operation, the TPS54361 device stops switching and the SS/TR must discharge to 54 mV when one of the following occurs: the VIN UVLO is exceeded, the EN pin pulled below 1.2 V, or a thermal shutdown event occurs.

The FB voltage follows the SS/TR pin voltage with a 42 mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.

Figure 28. Operation of SS/TR Pin When Starting

7.3.9 Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 29 using two TPS54361 devices. The power good is connected to the EN pin on the TPS54361 which enables the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 30 shows the results of Figure 29.

Figure 29. Schematic for Sequential Start-Up Sequence

Figure 30. Sequential Startup Using EN and PWRGD

Figure 31. Schematic for Ratiometric Start-Up Sequence

Figure 32. Ratiometric Startup Using Coupled SS/TR pins

Figure 31 shows a method for ratiometric start up sequence by connecting the SS/TR pins together. The regulator outputs ramps up and reaches regulation at the same time. When calculating the soft-start time the pullup current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.

Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 33 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the V_OUT2 slightly before, after or at the same time as V_OUT1. Equation 8 is the voltage difference between V_OUT1 and V_OUT2 at the 95% of nominal output regulation.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset (V_SSoffset) in the soft-start circuit and the offset created by the pullup current source (I_SS) and tracking resistors, the V_SSoffset and I_SS are included as variables in the equations.

To design a ratiometric start up in which the V_OUT2 voltage is slightly greater than the V_OUT1 voltage when V_OUT2 reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in a positive number for applications which the V_OUT2 is slightly lower than V_OUT1 when V_OUT2 regulation is achieved.

Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure the calculated R1 value from Equation 6 is greater than the value calculated in Equation 9 to ensure the device can recover from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage the V_SSoffset becomes larger as the soft-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in Figure 33.

Equation 6.

Equation 7.

Equation 8.

Equation 9.

Figure 34. Ratiometric Startup With Tracking Resistors

Figure 36. Simultaneous Startup With Tracking Resistor

Figure 35. Ratiometric Startup With Tracking Resistors

7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)

The switching frequency of the TPS54361 is adjustable over a wide range from 100 kHz to 2500 kHz by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage and minimum controllable on time must be considered. The minimum controllable on time is typically 100 ns which limits the maximum operating frequency in applications with high input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more detailed discussion of the maximum switching frequency is provided in Maximum Switching Frequency.

Equation 10.

Equation 11.

7.3.11 Synchronization to RT/CLK Pin

The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in Figure 37. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V and have a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of the SW is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit must be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected in parallel with an AC coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 37. The two resistors in series provide the default frequency setting resistance when the signal source is turned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. AC coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.

The first time the RT/CLK is pulled above the PLL threshold the TPS54361 switches from the RT resistor free-running frequency mode to the PLL synchronized mode. The internal 0.5-V voltage source is removed and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor mode to the PLL mode and locks onto the external clock frequency within 78 ms. During the transition from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the RT/CLK resistor.

The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and fault conditions. Figure 38, Figure 39 and Figure 40 show the device synchronized to an external system clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse-skip mode (Eco-Mode).

SPACER

Figure 37. Synchronizing to a System Clock

Figure 38. Plot of Synchronizing in CCM

Figure 40. Plot of Synchronizing in Eco-mode

Figure 39. Plot of Synchronizing in DCM

7.3.12 Maximum Switching Frequency

To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54361 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54361 uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the inductor current may exceed the peak current limit because of the high input voltage and the minimum controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down.

With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. Equation 13 calculates the maximum switching frequency at which the inductor current remains under control when V_OUT is forced to V_OUT(SC). The selected operating frequency must not exceed the calculated value.

Equation 12 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.

Equation 12.

Equation 13.

where

• I_O is the output current
• I_CL is the current limit
• R_dc is the inductor resistance
• V_IN is the maximum input voltage
• V_OUT is the output voltage
• V_OUT(SC) is the output voltage during short
• V_d is the diode voltage drop
• R_DS(on) is the switch ON-resistance
• t_ON is the controllable ON-time
• ƒ_DIV is the frequency divide equals (1, 2, 4, or 8)

7.3.13 Accurate Current Limit Operation

The TPS54361 implements peak current mode control in which the COMP pin voltage controls the peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the peak switch current limit. The TPS54361 provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown in Figure 41.

Figure 41. Current Limit Delay

7.3.14 Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output. Once the FB pin is between 93% and 106% of the internal voltage reference the PWRGD pin is deasserted and the pin floats. TI recommends a pullup resistor of 1 kΩ to a voltage source that is 5.5 V or less. A higher pullup resistance reduces the amount of current drawn from the pullup voltage source when the PWRGD pin is asserted low. A lower pullup resistance reduces the switching noise seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but with reduced current sinking capability. The PWRGD achieves full current-sinking capability as VIN input voltage approaches 3 V.

The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.

7.3.15 Overvoltage Protection

The TPS54361 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. In some applications, the power supply output voltage can increase faster than the response of the error amplifier output resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal voltage reference, the high-side MOSFET resumes normal operation.

7.3.16 Thermal Shutdown

The TPS54361 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature falls below 164°C, the device reinitiates the power-up sequence controlled by discharging the SS/TR pin.

7.3.17 Small Signal Model for Loop Response

Figure 42 shows a simplified equivalent model for the TPS54361 control loop which can be simulated to check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm_ea of 350 μS. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R_O and capacitor C_O model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small signal response of the overall loop. The dynamic loop response can be evaluated by replacing R_L with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation.

Figure 42. Small Signal Model for Loop Response

7.3.18 Simple Small Signal Model for Peak Current Mode Control

Figure 43 describes a simple small signal model that can be used to design the frequency compensation. The TPS54361 device power stage can be approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 42) is the power stage transconductance, gm_ps. The gm_ps for the TPS54361 device is 12 A/V. The low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in Equation 15.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 43. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 17).

Figure 43. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

Equation 14.

Equation 15.

Equation 16.

Equation 17.

7.3.19 Small Signal Model for Frequency Compensation

The TPS54361 uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 44. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small signal model in Figure 44. The open-loop gain and bandwidth are modeled using the R_O and C_O shown in Figure 44. See the application section for a design example using a Type 2A network with a low ESR output capacitor.

Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software tools to create a design based on the power supply requirements.

Figure 44. Types of Frequency Compensation

Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Equation 24.

Equation 25.

Equation 26.

Equation 27.