SLVSC39D November   2013  – January 2017 TPS54361

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skip Eco-Mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjust Undervoltage Lockout
      8. 7.3.8  Soft-Start/Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      11. 7.3.11 Synchronization to RT/CLK Pin
      12. 7.3.12 Maximum Switching Frequency
      13. 7.3.13 Accurate Current Limit Operation
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter With 7-V to 60-V Input and 5-V at 3.5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Soft-Start Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor Selection
          9. 8.2.1.2.9  Undervoltage Lockout Set Point
          10. 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Power Dissipation Estimate
          13. 8.2.1.2.13 Discontinuous Conduction Mode and Eco-Mode Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power Supply
      3. 8.2.3 Split-Rail Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Custom Design with WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VIN –0.3 65 V
EN –0.3 8.4
FB –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
BOOT-SW –0.3 8
SW –0.6 65
SW, 5-ns Transient –7 65
SW, 10-ns Transient –2 65
Operating junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage 4.5 60 V
VO Output voltage 0.8 58.8 V
IO Output current 0 3.5 A
TJ Junction Temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1) (2) TPS54361 UNIT
DPR (WSON)
10 PINS
RθJA Junction-to-ambient thermal resistance (standard board) 35.1 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 12.5 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 34.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 2.2 °C/W
RθJB Junction-to-board thermal resistance 12.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA must be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See the power dissipation estimate in Power Dissipation Estimate for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 4.5 60 V
Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V
Internal undervoltage lockout threshold hysteresis 325 mV
Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V 2.25 4.5 μA
Operating: nonswitching supply current FB = 0.9 V, TA = 25°C 152 200 μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
Input current Enable threshold +50 mV –4.6 μA
Enable threshold –50 mV –0.58 –1.2 –1.8
Hysteresis current –2.2 –3.4 –4.5 μA
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
ON-resistance VIN = 12 V, BOOT-SW = 6 V 89 190 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gm) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μS
Error amplifier transconductance (gm) during soft start –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μS
Error amplifier DC gain VFB = 0.8 V 10 000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source/sink V(COMP) = 1 V, 100-mV overdrive ±30 μA
COMP to SW current transconductance 12 A/V
CURRENT LIMIT
Current limit threshold All VIN and temperatures, open loop(1) 4.5 5.5 6.8 A
All temperatures, VIN = 12 V, open loop(1) 4.5 5.5 6.3
VIN = 12 V, TA = 25°C, open loop(1) 5.2 5.5 5.9
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V
SOFT START AND TRACKING (SS/TR PIN)
Charge current VSS/TR = 0.4 V 1.7 µA
SS/TR-to-FB matching VSS/TR = 0.4 V 42 mV
SS/TR-to-reference crossover 98% nominal 1.16 V
SS/TR discharge current (overload) FB = 0 V, VSS/TR = 0.4 V 354 µA
SS/TR discharge voltage FB = 0 V 54 mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low FB falling 90%
FB threshold for PWRGD high FB rising 93%
FB threshold for PWRGD low FB rising 108%
FB threshold for PWRGD high FB falling 106%
Hysteresis FB falling 2.5%
Output high leakage VPWRGD = 5.5 V, TA = 25°C 10 nA
ON-resistance IPWRGD = 3 mA, VFB < 0.79 V 45 Ω
Minimum VIN for defined output VPWRGD < 0.5 V, IPWRGD = 100 µA 0.9 2 V
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.

6.6 Timing Requirements

TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
MIN NOM MAX UNIT
RT/CLK
Minimum CLK input pulse width 15 ns

6.7 Switching Characteristics

TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SW
ton Minimum ON-time VIN = 23.7 V, VOUT = 5 V, IOUT = 3.5 A, RT = 39.6 kΩ, TA = 25°C 100 ns
CURRENT LIMIT
Current limit threshold delay 60 ns
RT/CLK
Switching frequency range using RT mode 100 2500 kHz
ƒSW Switching frequency RT = 200 kΩ 450 500 550 kHz
Switching frequency range using CLK mode 160 2300 kHz
RT/CLK falling edge to SW rising edge delay Measured at 500 kHz with an RT resistor in series 55 ns
PLL lock-in time Measured at 500 kHz 78 μs
ERROR AMPLIFIER
Enable to COMP active VIN = 12 V, TA = 25°C 540 µs

6.8 Typical Characteristics

TPS54361 C001_SLVSBO1.png
Figure 1. ON-Resistance vs Junction Temperature
TPS54361 C003_SLVSC39.png
Figure 3. Switch Current Limit vs Junction Temperature
TPS54361 C005_SLVSBO1.png
Figure 5. Switching Frequency vs Junction Temperature
TPS54361 C007_SLVSBO1.png
Figure 7. Switching Frequency vs RT/CLK Resistance
High-Frequency Range
TPS54361 C009_SLVSBO1.png
Figure 9. EA Transconductance During Soft Start vs Junction Temperature
TPS54361 C011_SLVSBO1.png
Figure 11. EN Pl Current vs Junction Temperature
TPS54361 C013_SLVSBO1.png
Figure 13. EN Pin Current Hysteresis vs Junction Temperature
TPS54361 C015_SLVSBO1.png
Figure 15. Shutdown Supply Current vs Junction Temperature
TPS54361 C017_SLVSBO1.png
Figure 17. VIN Supply Current vs Junction Temperature
TPS54361 C019_SLVSBO1.png
Figure 19. BOOT-SW UVLO vs Junction Temperature
TPS54361 C021_SLVSBO1.png
Figure 21. PWRGD ON-Resistance vs Junction Temperature
TPS54361 C024_SLVSBO1.png
Figure 23. SS/TR to FB Offset vs FB
TPS54361 C026_SLVSBO1.png
Figure 25. 5-V Start and Stop Voltage
(see Low Dropout Operation and Bootstrap Voltage (BOOT))
TPS54361 C002_SLVSBO1.png
Figure 2. Voltage Reference vs Junction Temperature
TPS54361 C004_SLVSC39.png
Figure 4. Switch Current Limit vs Input Voltage
TPS54361 C006_SLVSBO1.png
Figure 6. Switching Frequency vs RT/CLK Resistance
Low-Frequency Range
TPS54361 C008_SLVSBO1.png
Figure 8. EA Transconductance vs Junction Temperature
TPS54361 C010_SLVSBO1.png
Figure 10. EN Pin Voltage vs Junction Temperature
TPS54361 C012_SLVSBO1.png
Figure 12. EN Pin Current vs Junction Temperature
TPS54361 C014_SLVSBO1.png
Figure 14. Switching Frequency vs FB
TPS54361 C016_SLVSBO1.png
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
TPS54361 C018_SLVSBO1.png
Figure 18. VIN Supply Current vs Input Voltage
TPS54361 C020_SLVSBO1.png
Figure 20. Input Voltage UVLO vs Junction Temperature
TPS54361 C022_SLVSBO1.png
Figure 22. PWRGD Threshold vs Junction Temperature
TPS54361 C025_SLVSBO1.png
Figure 24. SS/TR to FB Offset vs Temperature