SLVSHZ2 July   2024 TPS544C27

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • VBD|33
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPS544C27 33-Pin VBD, WQFN-FCRLF Package (Top View)Figure 4-1 33-Pin VBD, WQFN-FCRLF Package (Top View)
TPS544C27 33-Pin VBD, WQFN-FCRLF Package (Bottom View)Figure 4-2 33-Pin VBD, WQFN-FCRLF Package (Bottom View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 26 G Ground pin, reference point for internal control circuitry
AGND 31 G Thermal pad internally tied to AGND. Connect this pad to board ground on PCB layout to enhance the thermal performance.
BOOT 20 P Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to the PHASE pin. A high temperature (X7R) 0.1μF or greater value ceramic capacitor is recommended.
EN 21 I Enable pin, an active-high input pin that, when asserted high, causes the VR to begin soft-start sequence for the output voltage rail. When de-asserted low, the VR de-asserts VRRDY and begins the shutdown sequence of the output voltage rail and continue to completion.
GOSNS 25 I Negative input of the differential remote sense circuit, connect to the ground sense point on the load side
I_IN_M 4 I Negative input of the differential input current sense. Connect to PVIN side of input current sense resistor. If input current sense not used, connect directly to I_IN_P and PVIN.
I_IN_P 3 I Positive Input of the differential input current sense. Connect to the input side of input current sense resistor. If input current sense not used, connect directly to I_IN_M and PVIN.
PGND 8-9, 16-17 G Power ground for the internal power stage
PGND 33 G Thermal pad internally tied to PGND. Connect this pad to board ground on PCB layout to enhance the thermal performance.
PHASE 19 O Return for high-side MOSFET driver. Shorted to SW internally. Connect the BOOT pin bypass capacitor to this pin.
PMB_ADDR / IMON / VORST# 23 I/O Multi-purpose pin. During the device initialization, the PMBus address of the controller is set by tying an external resistor between this pin and AGND. For proper resistor detection, do not load this pin with more than 20pF during the device initialization at VCC power-up. DC_LL, VBOOT, and OFFSET source 0 or 1 are selected as well. After device initialization, this pin can be used as an analog current monitor output. This pin is a current sense of low-side MOSFET. The analog IMON feature is enabled via the EN_AIMON bit. When using the IMON feature, do not load this pin with more than 50pF. This pin also performs a VOUT reset function that can be enabled via the EN_VORST bit. If the EN_VORST bit is set, the analog IMON output is disabled.
PMB_CLK 30 I PMBus serial clock pin
PMB_DATA 1 I/O PMBus bi-directional serial data pin
PVIN 7, 18 P Power input for both the power stage and the analog circuit. PVIN is the input of the internal VCC LDO.
PVIN 32 P Pad internally tied to PVIN. Connect this pad to the power input voltage in the PCB layout and use vias to connect to internal layers to reduce AC and DC parasitics in the PCB layout.
SMB_ALERT# / CAT_FAULT# / PINALRT# 22 O Multi-purpose open-drain pin. 1. SMB_ALERT# is PMBus serial active low alert line. 2. PINALRT# function (active low) 3. CAT_FAULT# active low Catastrophic Fault indicator. The functionality can be selected via the SEL_ALRT_FN field in the PMBus (D0h) SYS_CFG_USER1 command..
SV_ALERT# 29 O SVID active low ALERT# signal. This output is asserted to indicate the status of the VR has changed.
SV_CLK 27 I SVID clock pin
SV_DIO 28 I/O SVID bi-directional data pin
SW 10-15 O Output switching terminal of the power converter. Connect these pins to the output inductor.
VCC 5 I 5V bias for internal circuitry. Connect to VDRV or power from same external 5V bias. Bypass to AGND with minimum 1.0μF, 10V ceramic capacitor
VDRV 6 P Internal LDO output and also input for gate driver circuit. An external 5V bias can be connected to this pin to save the power losses on the internal LDO.
VOSNS 24 I Positive input of the differential remote sense circuit, connect to the Vout sense point on the load side
VRRDY 2 O Voltage regulator “Ready” output signal. The VRRDY indicator is asserted when the controller is ready to accept SVID commands after EN is asserted. VRRDY is also be de-asserted low when a shutdown fault occurs. This open-drain output requires an external pullup resistor.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.