SLVSI40 August   2024 TPS544E27

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPS544E27 RXX 37-Pin WQFN-FCRLF Package (Top View)Figure 4-1 RXX 37-Pin WQFN-FCRLF Package (Top View)
TPS544E27 RXX 37-Pin WQFN-FCRLF Package (Bottom View)Figure 4-2 RXX 37-Pin WQFN-FCRLF Package (Bottom View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 32 G Ground pin, reference point for internal control circuitry
BOOT 26 P Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to PHASE pin. A high temperature (X7R) 0.1μF or greater value ceramic capacitor is recommended.
EN 27 I Enable pin, an active-high input pin that, when asserted high, causes the VR to begin the soft-start sequence for the output voltage rail. When deasserted low, the VR deasserts VRRDY and begins the shutdown sequence of the output voltage rail and continue to completion.
GOSNS 31 I Negative input of the differential remote sense circuit, connect to the ground sense point on the load side.
I_IN_M 4 I Connect to the negative side of the local input power sense resistor. Input voltage for VIN telemetry is also sensed at this pin. If input power sensing is not being used then connect I_IN_P and I_IN_M together, and connect both to PVIN for VIN telemetry. The pins can also be connected to ground or another voltage if VIN telemetry is not needed.
I_IN_P 3 I Connect to the positive side of a local input power sense resistor. If input power sensing is not being used then connect I_IN_P to I_IN_M.
NC 6, 37 — Not connected. These pins are floating internally.
PGND 7 – 10, 19 G Power ground for the internal power stage
PHASE 25 O Return for high-side MOSFET driver. Shorted to SW internally. Connect the BOOT pin bypass capacitor to this pin.
PMB_ADDR / IMON / VORST# 29 I/O Multipurpose pin. During the device initialization, the PMBus address of the controller is set by tying an external resistor between this pin and AGND. For proper resistor detection, do not load this pin with more than 20pF during the device initialization at VCC power-up. DC_LL, VBOOT and OFFSET source 0 or 1 are selected as well. After device initialization, this pin can be used as an analog current monitor output. This pin is a current sense of low-side MOSFET. The analog IMON feature is enabled through the EN_AIMON bit. When using the IMON feature, do not load this pin with more than 50pF. This pin also performs a VOUT reset function that can be enabled through the EN_VORST bit. If the EN_VORST bit is set, the analog IMON output is disabled.
PMB_CLK 36 I PMBus serial clock pin
PMB_DATA 1 I/O PMBus bi-directional serial data pin
PVIN 20 – 24 P Power input for both the power stage and the analog circuit. PVIN is the input of the internal VCC LDO.
SMB_ALERT# / PINALRT# / CAT_FAULT# 28 O Multipurpose open-drain output pin. 1. SMB_ALERT# is PMBus serial active low alert line. 2. PINALRT# function (active low) 3. CAT_FAULT# active low Catastrophic Fault indicator. The functionality can be selected through the SEL_ALRT_FN field in the PMBus (D0h) SYS_CFG_USER1 command.
SV_ALERT# 35 O SVID active low ALERT# signal. This output is asserted to indicate the status of the VR has changed.
SV_CLK 34 I SVID clock pin
SV_DIO 33 I/O SVID bi-directional data pin
SW 11 – 18 O Output switching terminal of the power converter. Connect these pins to the output inductor.
VCC/VDRV 5 P Internal LDO output and also input for gate driver circuit. An external 5V bias can be connected to this pin to save the power losses on the internal LDO. The voltage source on this pin powers both the internal control circuitry and gate driver.
VOSNS 30 I Positive input of the differential remote sense circuit, connect to the VOUT sense point on the load side
VRRDY 2 O Voltage regulator “Ready” output signal. The VRRDY indicator is asserted when the controller is ready to accept SVID commands after EN is asserted. VRRDY is also deasserted low when a shutdown fault occurs. This open-drain output requires an external pullup resistor.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.