SLVSBO1G July   2013  – June 2021 TPS54561

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft Start/Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      11. 7.3.11 Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Accurate Current Limit Operation
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Slow Start Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor Selection
          9. 8.2.1.2.9  Undervoltage Lockout Set Point
          10. 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Power Dissipation Estimate
          13. 8.2.1.2.13 Safe Operating Area
          14. 8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
      3. 8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design with WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9 Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 7-4 using two TPS54561 devices. The power good is Connected to the EN pin on the TPS54561 which will enable the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply will provide a 1-ms start up delay. Figure 7-5 shows the results of Figure 7-4.

GUID-39A59933-41E7-4E30-8FE1-F7FC0D59DAD2-low.gifFigure 7-4 Schematic for Sequential Start-Up Sequence
GUID-3FEB5AB8-10FD-4276-B92C-ADD67B480D6E-low.gifFigure 7-5 Sequential Startup using EN and PWRGD
GUID-EEFD6488-E5EC-4B7B-A6D1-07BEAD97A8C0-low.gifFigure 7-6 Schematic for Ratio-Metric Start-Up Sequence
GUID-A59D1C39-1D0A-4B14-9889-592DE515A1AE-low.gifFigure 7-7 Ratio-Metric Startup using Coupled SS/TR pins

Figure 7-6 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the soft start time the pull up current source must be doubled in Equation 5. Figure 7-7 shows the results of Figure 7-6.

GUID-CF0741CB-1196-469E-9B3A-CC67CEFD0431-low.gifFigure 7-8 Schematic for Ratio-Metric and Simultaneous Start-Up Sequence

Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 7-8 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and Vout2 at the 95% of nominal output regulation.

The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset (VSSOFFSET) in the soft start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the VSSOFFSET and ISS are included as variables in the equations.

To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 6 through Equation 8 for deltaV. Equation 8 will result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.

Since the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors ensures that the device will restart after a fault. The calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9 to ensure the device recovers from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSSOFFSET becomes larger as the soft start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.5 V for a complete handoff to the internal voltage reference.

Equation 6. GUID-255B3784-8A9A-4D9F-B526-54892E1682D5-low.gif
Equation 7. GUID-B63C28FF-366E-4ED0-B025-CDF49DCBC91E-low.gif
Equation 8. GUID-49C03707-25FD-4345-A7FE-EEAE64D704EE-low.gif
Equation 9. GUID-46E71311-CB63-4E09-879B-7C87950DDBFC-low.gif
GUID-71A118C0-D3E3-483C-B3BD-F60C28ED11BC-low.gifFigure 7-9 Ratio-Metric Startup with Tracking Resistors
GUID-0118BA5B-D011-4DFB-BB64-D010BA8433B8-low.gifFigure 7-11 Simultaneous Startup with Tracking Resistor
GUID-5CC4E6E5-062A-40B5-811C-AD82F087ADC5-low.gifFigure 7-10 Ratio-Metric Startup with Tracking Resistors