SLVSAE9F November   2010  – May 2019 TPS54618

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Frequency Shift
      13. 7.3.13 Reverse Overcurrent Protection
      14. 7.3.14 Synchronize Using the RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Simple Small Signal Model for Peak Current Mode Control
      2. 7.4.2 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Step One: Select the Switching Frequency
        3. 8.2.2.3 Step Two: Select the Output Inductor
        4. 8.2.2.4 Step Three: Choose the Output Capacitor
        5. 8.2.2.5 Step Four: Select the Input Capacitor
        6. 8.2.2.6 Step Five: Choose the Soft-Start Capacitor
        7. 8.2.2.7 Step Six: Select the Bootstrap Capacitor
        8. 8.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
          1. 8.2.2.8.1 Output Voltage Limitations
        9. 8.2.2.9 Step Nine: Select Loop Compensation Components
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Developmental Support
      2. 11.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.9 Step Nine: Select Loop Compensation Components

There are several industry techniques used to compensate DC–DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54618. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.

To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and Equation 37. For COUT, the derated capacitance value is 82.5 µF. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 6.43 kHz and fzmod is 643 kHz. Equation 38 is the geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the switching frequency. Equation 38 yields 64.3 kHz and Equation 39 gives 56.7 kHz. The lower value of Equation 38 or Equation 39 is the maximum recommended crossover frequency. For this example, a lower fc value of 40 kHz is specified. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed).

Equation 36. TPS54618 comp_eq1_lvs946.gif

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Equation 37. TPS54618 comp_eq2_lvs946.gif

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Equation 38. TPS54618 comp_eq3_lvs946.gif

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Equation 39. TPS54618 comp_eq4_lvs946.gif

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The compensation design takes the following steps:

  1. Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value of the compensation network. In this example, the anticipated crossover frequency (fc) is 40 kHz. The power stage gain (gmps) is 25 A/V and the error amplifier gain (gmea) is 245 μA/V.
    2. Equation 40. TPS54618 eq26_r3_lv46.gif
  2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The capacitor of the compensation network can be calculated from Equation 41.
    3. Equation 41. TPS54618 Eq_C4_lvsae9.gif
  3. An additional pole can be added to attenuate high-frequency noise. In this application, it is not necessary to add it.

From the previously listed procedures, the compensation network includes a 7.50-kΩ resistor and a
3300-pF capacitor.