SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
| CMD Address: | 7Bh |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Back-up: | Yes |
| Updates: | On-the-fly |
The STATUS_IOUT command returns one data byte with contents as follows. None of these bits is affected by the state of SMBALERT_MASK. However, if the corresponding fault/warning disable bits in the FAULT_CTRL register is set, then the corresponding status bits will also be blocked in addition to blocking the response from that fault. All supported bits may be cleared either by CLEAR_FAULTS, turning on the output through the mechanism programmed into ON_OFF_CONFIG, or individually by writing 1b to the STATUS_IOUT register in their position, per the PMBus 1.3.1 Part II specification section 10.2.3.
OCF[7] and OCW[5] share a single NVM bit for changing the shared default NVM masking capability. Thus, overcurrent fault and warning SMBALERT masking default can be set and stored to NVM by the user; however, since they share a single NVM bit, the default ability or inability (masking) to set SMBALERT is always common/same after a restore from NVM or power-cycle. In contrast, dynamically setting the two smb_alert mask bits different/independently is allowed and is the only way the two mask settings can be different. Upon power-cycle/NVM-restore the two SMB_ALERT mask settings will revert to the same setting. The initial default is that both will trigger SMBALERT (as noted in the SMBALERT_MASK command default definition). The actual NVM bit is associated with OCW [5] – so, the value in this bit position’s SMBALERT_MASK bit is what is stored/restored to/from NVM.
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW1C | R | RW1C | RW1C | R | R | R | R |
| OCF | OCUV | OCW | UCF | 0 | 0 | 0 | 0 |
| LEGEND: R/W1C = Read/Write 1 to clear; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | OCF Supported | RW1C | 0b | This latched bit is set to 1 upon detection of an IOUT OCF event as configured by the IOUT_OC_FAULT_LIMIT. Not supported and always set to 0. |
| 6 | OCUV | R | 0b | VOUT UV caused by OCL. 0b: Latched flag indicating the IOUT_OC_LV_FAULT has NOT occurred. 1b: Latched flag indicating IOUT_OC_LV_FAULT has occurred. This bit is set when the output voltage is below the IOUT_OC_LV_FAULT_LIMIT AND the output current exceeds the IOUT_OC_FAULT_LIMIT. This bit cannot be cleared by writing to 1b to it. It is cleared by writing 1b to VOUT_UVF in STATUS_VOUT. |
| 5 | OCW | RW1C | 0b |
0b: Latched flag indicating an output overcurrent warning has NOT occured. 1b: Latched flag indicating an output overcurrent warning has occured. |
| 4 | UCF | RW1C | 0b | This latched bit is set to 1 upon detection of IOUT UC fault.
0b: Latched flag indicating an output undercurrent fault has NOT occured. 1b: Latched flag indicating an output undercurrent fault has occured. |
| 3:0 | Not supported | R | 0000b | Not supported and always set to 0. |