SLVSHH4 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address | 49h |
| Write Transaction: | N/A |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (2 bytes) |
| NVM Backup: | No |
| Updates: | On-the-fly |
The IOUT_OC_LV_FAULT_RESPONSE register defines the response to a UV fault declaration when the part is operating in current-limit conditions. Upon detecting a fault, the device:
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R | R | R | R | R | R | R |
| 0 | IGNRZ_OC_LV | RS_OC_LV | TD__OC_LV | ||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | 0 | R | 0b | Not used and always set to 0. |
| 6 | IGNRZ_OC_LV | R | 1b | Output
overvoltage response setting during OC. These bits are copied directly from VOUT_UV_FAULT_RESPONSE and have read only access in this register. 0b: The device continues operation (i.e., ignores the fault) without interruption (note that the bit[6] IGNRZ_UV is active low so that when IGNRZ_OV=0, the fault is ignored). 1b: The device continues to operate for the delay time specified by TD_OC_LV. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting. |
| 5:3 | RS_OC_LV | R | NVM | Output voltage
under voltage retry setting. These bits are copied directly from VOUT_UV_FAULT_RESPONSE and have read only access in this register. 000b: Latch-off after the fault. The device remains disabled until the fault is cleared. A VCC power cycle or EN toggle can restart the power conversion. 111b: Automatically restart after a 52ms delay, without limitation on the number of restart attempts, until it is commanded off or bias power is removed or another fault condition causes the unit to shutdown. Any value other than 000b or 111b will not be accepted and such an attempt shall be considered as invalid data or usupported data (ivd) and the device will respond as described in ivd. Since all 3 bits must be the same, only one bit (bit 5) is stored in EEPROM. |
| 2:0 | TD_OC_LV | R | 000b | Output under
voltage retry response time delay setting. These bits are copied directly from VOUT_UV_FAULT_RESPONSE and have read only access in this register. The hiccup time is always 52ms, but the response can be delayed with the following settings in bits [1:0]. If the fault condition goes away before the delay counter expires, then the delay counter is reset to 0, and the output is not disabled. Bit 2 is read only and always 0. 000b: 2 us 001b: 16 us 010b: 64 us 011b: 256 us |