SLVSHN0 September   2024 TPS548B23

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 7.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 7.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 7.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 7.3.4  Enable
      5. 7.3.5  Soft Start
      6. 7.3.6  Power Good
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Remote Sense
      9. 7.3.9  Low-side MOSFET Zero-Crossing
      10. 7.3.10 Current Sense and Positive Overcurrent Protection
      11. 7.3.11 Low-side MOSFET Negative Current Limit
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting Point
        2. 8.2.2.2 Choose the Switching Frequency
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Choose the Input Capacitors (CIN)
        6. 8.2.2.6 VCC Bypass Capacitor
        7. 8.2.2.7 BOOT Capacitor
        8. 8.2.2.8 PG Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • VAN|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Overvoltage and Undervoltage Protection

The device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage events. The OVP function enables when the output is enabled. The UVP function enables after the soft-start period is complete.

After soft-start is complete, if the FB voltage becomes lower than 80% of the VREF voltage, the UVP comparator trips and an internal UVP delay counter begins counting. After the 70µs UVP delay time, depending on the selected fault recovery mode, the device either hiccups and re-starts after a sleep time of 7 × the soft-start period or latches off both high-side and low-side MOSFETs. The latch-off fault can be cleared with a reset of VIN or by toggling the EN pin.

When the output is enabled, the FB voltage must rise above the 92.5% PG low-to-high threshold to clear the UVP comparator. If the FB voltage does not exceed the 92.5% threshold by the end of the soft-start period, the device responds to the undervoltage event.

During the UVP delay time, if the FB voltage becomes higher than the 92.5% PG low-to-high threshold, the undervoltage event is cleared and the timer is reset to zero. When the output voltage falls below the 80% UVP threshold again, the 70-μs timer re-starts.

When the FB voltage becomes higher than 116% of the VREF voltage, the OVP comparator trips and the circuit latches the fault condition and drives the PG pin low. The high-side MOSFET turns off and the low-side MOSFET turns on until reaching a negative current limit INOCL. Upon reaching the negative current limit, the low-side MOSFET is turned off, and the high-side MOSFET is turned on again, for a proper on-time (determined by VO/VIN/fSW). The device operates in this mode until the output voltage is pulled down under the UVP threshold. The device then responds to the undervoltage event as described above.

If there is an overvoltage condition prior to the output being enabled (such as a high prebiased output), the device responds to the overvoltage event as described above at the beginning of the soft-start period. The device waits until the completion of the soft-start period for UVP to be enabled, and depending on the selected fault recovery mode, the device either hiccups and re-starts after a sleep time of 7 × the soft-start period or latches off .