When the EN pin voltage rises above the enable threshold voltage (typically 1.22 V) and V_IN rises above the V_IN UVLO rising threshold, the device enters its internal power-up sequence. The EN to first switching delay is specified in the Start-up section in the Electrical Characteristics table.

When using the internal VCC LDO, the internal power-up sequence includes three sequential steps. During the first period, the VCC voltage is charged up on a VCC bypass capacitor by an 11-mA current source. The length of this VCC LDO start-up time varies with the capacitance on the VCC pin. However, if the V_IN voltage ramps up very slowly, the VCC LDO output voltage will be limited by the V_IN voltage level, thus the VCC LDO start-up time can be extended longer. Since the VCC LDO start-up time is relatively long, the internal V_INTREF build-up happens and finishes during this period. Once the VCC voltage crosses above VCC UVLO rising threshold (typically 2.87 V), the device moves to the second step, power-on delay. The MODE pin setting detection, SS/REFIN pin detection, and control loop initialization are finished within this 285-μs delay. Soft-start ramp starts when the 285-μs power-on delay finishes. During the soft-start ramp power stage, switching does not happen until the SS/REFIN pin voltage reaches 50 mV. This introduces a SS delay that varies with the external capacitance on the SS/REFIN pin.

Figure 7-1 shows an example where the V_IN UVLO rising threshold is satisfied earlier than the EN rising threshold. In this scenario, the V_CC UVLO rising threshold becomes the gating signal to start the internal power-up sequence, and the sequence between VIN and EN does not matter.

When using an external bias on the VCC pin, the internal power-up sequence still includes three sequential steps. The first period is much shorter since VCC voltage is built up already. A 100-µs period allows the internal references to start up and reach regulation points. This 100-µs period includes not only the 0.6-V V_INTREF, but also all of the other reference voltages for various functions. The device then moves to the second step, power-on delay. The MODE pin setting detection, SS/REFIN pin detection, and control loop initialization are finished within this 285-μs delay. Soft-start ramp starts when the 285-μs power-on delay finishes. During the soft-start ramp power stage, switching does not happen until the SS/REFIN pin voltage reaches 50 mV. This introduces a SS delay that varies with the external capacitance on the SS/REFIN pin.

Figure 7-2 shows an example where the V_IN UVLO rising threshold and EN rising threshold are satisfied later than the V_CC UVLO rising threshold. In this scenario, the VIN UVLO rising threshold or EN rising threshold, whichever is satisfied later, becomes the gating signal to start the internal power-up sequence.

Figure 7-1 Internal Power-Up Sequence Using Internal LDO

Figure 7-2 Internal Power-Up Sequence Using External Bias

The EN pin has an internal filter to avoid unexpected ON or OFF due to small glitches. The time constant of this RC filter is 5 µs. For example, when applying a 3.3-V voltage source on the EN pin that jumps from 0 V to 3.3 V with an ideal rising edge, the internal EN signal will reach 2.086 V after 5 µs, which is 63.2% of applied 3.3-V voltage level.

A internal pulldown resistor is implemented between the EN pin and AGND pin. To avoid impact to the EN rising/falling threshold, this internal pulldown resistor is set to 6.5 MΩ. With this pulldown resistor, floating the EN pin before start-up keeps the device under disabled state. During nominal operation when the power stage switches, this large internal pulldown resistor may not have enough noise immunity to hold EN the pin low.

The maximum recommended operating condition for the EN pin is 5.5 V. Do not connect the EN pin to the VIN pin directly.