SLVSGM2 March   2023 TPS548C26

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC and VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Fixed PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Set the Output Voltage
      4. 7.3.4  Differential Remote Sense and Feedback Divider
      5. 7.3.5  Start-up and Shutdown
      6. 7.3.6  Loop Compensation
      7. 7.3.7  Set Switching Frequency and Operation Mode
      8. 7.3.8  Switching Node (SW)
      9. 7.3.9  Overcurrent Limit and Low-side Current Sense
      10. 7.3.10 Negative Overcurrent Limit
      11. 7.3.11 Zero-Crossing Detection
      12. 7.3.12 Input Overvoltage Protection
      13. 7.3.13 Output Undervoltage and Overvoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Powering the Device from a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC and VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 PG Pullup Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS548C26 Evaluation Board
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RXX 37-pin WQFN-FCRLF Package (Top View)
Figure 5-2 RXX 37-pin WQFN-FCRLF Package (Bottom View)
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
AGND 32 G Ground pin, reference point for internal control circuitry.
AVIN 3 P Supply rail for the internal VCC LDO. Connect a 1 μF, 25V ceramic capacitor to AGND to bypass this pin.
BOOT 26 P Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to PHASE pin. A high temperature (X7R) 0.1 μF or greater value ceramic capacitor is recommended.
DNC 6 — Do Not Connect (DNC) pin. This pin is the output of internal circuitry and must be floating. Pin 6 and pin 37 can be shorted together but NO any other PCB connection is allowed on pin 6.
EN 27 I Enable pin, an active-high input pin that, when asserted high, causes the converter to begin the soft-start sequence for the output voltage rail. When de-asserted low, the converter de-asserts PG pin and begins the shutdown sequence of the output voltage rail and continue to completion.
FB 30 I Positive input of the differential remote sense amplifier, connect to the center point of an external voltage divider. The voltage divider must be connected to output remote sense point.
GOSNS 31 I Negative input of the differential remote sense circuit, connect to the ground sense point on the load side.
ILIM 1 I Overcurrent limit selection pin. Connect a resistor to AGND to select the overcurrent limit threshold.
MODE 36 I The MODE pin selects the switching frequency and sets the operation mode to FCCM or DCM, by connecting a resistor to AGND.
SS 29 I The SS pin selects the soft-start time, internal compensation and the fault response, by connecting a resistor to AGND.
NC 33, 34, 35 — No connection (NC) pin. There is no active circuit connected inside the IC. These pins can be connected to ground plane or left open.
NC 37 — No connection (NC) pin. This pin is floating internally. Pin 37 and pin 6 can be shorted together.
PG 2 O Power-good output signal. The PG indicator is asserted when the output voltage reaches the regulation. The PG indicator de-asserts low when the EN pin is pulled low or a shutdown fault occurs. This open-drain output requires an external pullup resistor.
PGND 7–10, 19 G Power ground for the internal power stage.
PHASE 25 — Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap capacitor from BOOT pin to this pin.
PVIN 20–24 P Power input for both the power stage. PVIN is the input of the internal VCC LDO as well.
SW 11–18 O Output switching terminal of the power converter. Connect these pins to the output inductor.
VCC 4 P Internal VCC LDO output and also the input for the internal control circuitry. A 2.2 μF (or 1 μF), at least 6.3 V rating ceramic capacitor is required to be placed from VCC pin to AGND for decoupling.
VDRV 5 P Power supply input for gate driver circuit. A 2.2 μF (or 4.7 μF), at least 6.3 V rating ceramic capacitor is required to be placed from VDRV pin to PGND pins to decouple the noise generated by driver circuitry. An external 5 V bias can be connected to this pin to save the power losses on the internal LDO.
VOSNS 28 I Output voltage sense point for internal on-time generation circuitry. Shorting this pin directly to VOUT sense point is recommended. Adding any resistance higher than 51 Ω between VOUT sense point and the VOSNS pin shifts switching frequency higher than the desired setting. Contact Texas Instruments if a resistor has to be placed between VOUT sense point and the VOSNS pin.