SLVSGM2 March   2023 TPS548C26

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC and VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Fixed PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Set the Output Voltage
      4. 7.3.4  Differential Remote Sense and Feedback Divider
      5. 7.3.5  Start-up and Shutdown
      6. 7.3.6  Loop Compensation
      7. 7.3.7  Set Switching Frequency and Operation Mode
      8. 7.3.8  Switching Node (SW)
      9. 7.3.9  Overcurrent Limit and Low-side Current Sense
      10. 7.3.10 Negative Overcurrent Limit
      11. 7.3.11 Zero-Crossing Detection
      12. 7.3.12 Input Overvoltage Protection
      13. 7.3.13 Output Undervoltage and Overvoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Powering the Device from a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC and VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 PG Pullup Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS548C26 Evaluation Board
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Layout Guidelines

Layout is critical for good power supply design. Layout example shows the recommended PCB layout configuration. A list of PCB layout considerations using the device is listed as follows:

  • Place the power components (including input and output capacitors, the inductor, and the IC) on the top side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid ground inner plane.
  • PVIN-to-PGND decoupling capacitors are important for FET robustness. Besides the large volume 0603 or 0805 ceramic capacitors, TI highly recommends a 0.1-µF, 0402 ceramic capacitor with 25-V / X7R rating on PVIN pin 20 (top layer) to bypass any high frequency current in PVIN to PGND loop. TI recommends the 25-V rating, but can be lowered to 16-V rating for an application with tightly regulated 12-V input bus.
  • When one or more PVIN-to-PGND decoupling capacitors are placed on bottom layer, extra impedance is introduced to bypass IC PVIN node to IC PGND node. Placing at least 3 times PVIN vias on PVIN pad (formed by pin 20 to pin 24) and at least nine times PGND vias on the thermal pad (underneath of the IC) is important to minimize the extra impedance for the bottom layer bypass capacitors.
  • Except the PGND vias underneath the thermal pad, at least four PGND vias are required to be placed as close as possible to the PGND pin 7 to pin 10. At least two PGND vias are required to be placed as close as possible to the PGND pin 19. This action minimizes PGND bounces and also lowers thermal resistance.
  • Place the VDRV-to-PGND decoupling capacitor as close as possible to the device. TI recommends a 2.2-µF/6.3 V/X7R/0603 or 4.7-µF/6.3 V/X6S/0603 ceramic capacitor. The voltage rating of this bypass capacitor must be at least 6.3 V but no more than 10 V to lower ESR and ESL. The recommended capacitor size is 0603 to minimize the capacitance drop due to DC bias effect. Ensure the VDRV to PGND decoupling loop is the smallest and ensure the routing trace is wide enough to lower impedance.
  • As the input of VCC LDO, connect a 1-µF, 25-V rated ceramic capacitor to AGND for the bypassing of the AVIN pin. TI recommends the 25-V rating is recommended but can be lowered to 16-V rating for an application with tightly regulated 12-V input bus.
  • Connect a 2.2-µF, 6.3-V (or 10 V) rated ceramic capacitor to AGND for the bypassing of the VCC pin. Placing a 1-Ω resistor between the VCC pin and VDRV pin forms a RC filter on VCC pin, which greatly reduces the noise impact from power stage driver circuit.
  • For remote sensing, the connections from FB voltage divider resistors to the remote location must be a pair of PCB traces with at least 12 mil trace width, and must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher on the sensing location. The ground connection of the remote sensing signal must be connected to the GOSNS pin. The VOUT connection of the remote sensing signal must be connected to the VOSNS pin and the top feedback resistor RFB_top. To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any noise sources such as inductor and SW node, or high frequency clock lines. TI recommends to shield the pair of remote sensing lines with ground planes above and below.
  • For single-end sensing, connect the FB voltage divider resistors to a high-frequency local bypass capacitor of 0.1 μF or higher, and short GOSNS to AGND with shortest trace.
  • The AGND pin 32 must be connected to a solid PGND plane. TI recommends to place AGND via close to pin 32 to route AGND from top layer to bottom layer, and then connect the AGND trace to the PGND vias (underneath IC) through either a net-tie or a 0-Ω resistor on the bottom layer.
  • Connecting a resistor from pin 1 (ILIM) to AGND sets the OCL threshold. Connecting a resistor from pin 29 (SS) to AGND sets soft-start time, internal compensation, and fault response. Connecting a resistor from pin 36 (MODE) to AGND sets the switching frequency and the operation mode. TI requires not to have any capacitor on these 3 pins (ILIM, SS, and MODE). A capacitor on any of these 3 pins likely leads to a wrong detection result.
  • Pin 6 (DNC) is a Do-Not-Connect pin. Pin 6 can be shorted to pin 37, which is an NC pin (No internal Connection). Do not connect pin 6 to any other net including ground.