SLVSHC5B November   2023  – July 2024 TPS548D26

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using an External Bias on the VCC and VDRV Pin
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Fixed VCC_OK UVLO
        2. 6.3.2.2 Fixed VDRV UVLO
        3. 6.3.2.3 Fixed PVIN UVLO
        4. 6.3.2.4 Enable
      3. 6.3.3  Set the Output Voltage
      4. 6.3.4  Differential Remote Sense and Feedback Divider
      5. 6.3.5  Start-Up and Shutdown
      6. 6.3.6  Loop Compensation
      7. 6.3.7  Set Switching Frequency and Operation Mode
      8. 6.3.8  Switching Node (SW)
      9. 6.3.9  Overcurrent Limit and Low-side Current Sense
      10. 6.3.10 Negative Overcurrent Limit
      11. 6.3.11 Zero-Crossing Detection
      12. 6.3.12 Input Overvoltage Protection
      13. 6.3.13 Output Undervoltage and Overvoltage Protection
      14. 6.3.14 Overtemperature Protection
      15. 6.3.15 Power Good
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 6.4.3 Powering the Device From a 12-V Bus
      4. 6.4.4 Powering the Device From a Split-Rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Inductor Selection
        2. 7.2.3.2 Input Capacitor Selection
        3. 7.2.3.3 Output Capacitor Selection
        4. 7.2.3.4 VCC and VRDV Bypass Capacitor
        5. 7.2.3.5 BOOT Capacitor Selection
        6. 7.2.3.6 PG Pullup Resistor Selection
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance on TPS548D26 Evaluation Board
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Integrated 4.0mΩ and 1.0mΩ MOSFETs for 40A continuous current operation
  • Supports external 5V bias improving efficiency and enabling 2.7V minimum input voltage
  • 0.6V to 5.5V output voltage range
  • Precision voltage reference and differential remote sense for high output accuracy
    • ±0.5% VOUT tolerance from 0°C to 85°C TJ
    • ±1% VOUT tolerance from –40°C to 125°C TJ
  • D-CAP+™ control topology with fast transient response, supporting all ceramic output capacitors
  • Selectable internal loop compensation through SS pin
  • Selectable cycle-by-cycle valley current limit
  • Selectable operation frequency 0.6MHz to 1.2MHz with DCM or FCCM operation
  • Safe start-up into prebiased outputs
  • Programmable soft-start time from 0.75ms to 6ms
  • Open-drain power-good output (PG)
  • Overcurrent, overvoltage, undervoltage, and overtemperature protections with selectable hiccup or latch-off response
  • 5mm × 6mm, 37-pin WQFN-FCRLF package