SLVS847A November 2008 – December 2016 TPS54917
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
TPS54917 is a synchronous buck converter. It can convert an input voltage of 3 V to 4 V to a lower voltage. Maximum output current is 9 A.
Figure 10 shows the schematic diagram for a typical TPS54917 application. The TPS54917 (U1) can provide up to 9 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the exposed thermal PowerPAD underneath the integrated circuit (TPS54917) package must be soldered to the printed-circuit board.
Table 2 lists the design specifications for this application example.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT CHARACTERSTICS | |||||||
VIN | Input voltage | 3 | 3.3 | 4 | V | ||
OUTPUT CHARACTERSTICS | |||||||
VOUT | Output voltage 1 | VIN = Nom, IOUT = Nom | 1.8 | V | |||
IOUT | 0 | 9 | |||||
TRANSIENT RESPONSE | |||||||
ΔVOUT | Change from load transient | ΔIOUT = 4.5 A | 50 | mV | |||
Settling time | to 1% of VOUT | 0.5 | ms | ||||
SYSTEMS CHARACTERSTICS | |||||||
fSW | Switching frequency | 1600 | kHz |
The values for the components used in this design example were selected for best load transient response and small PCB area. Additional design information is available at www.ti.com.
The input voltage is a nominal 3.3 VDC. The input filter capacitors (C1 and C2) are 10-µF ceramic capacitors (MuRata). C12 is a 0.01-µF ceramic capacitor that provides high-frequency decoupling of the TPS54917 from the input supply. C1, C2, and C12 must be placed as close as possible to the device. Input ripple current is shared among C1, C2, and C12.
The values for these components are selected to provide fast transient response times.
The resistor divider network of R1 and R2 sets the output voltage for the circuit at 1.8 V. R1 along with R6, R7, C5, C7, and C10 forms the loop compensation network for the circuit. For this design, a Type-3 topology is used. The feedback loop is compensated so that the unity gain frequency is approximately 40 kHz.
In the application circuit, RT is grounded through a 27.4-kΩ resistor to select the operating frequency of 1.6 MHz. To set a different frequency, place a 27-kΩ to 180-kΩ resistor between RT (pin 29) and analog ground or leave RT floating to select the default of 350 kHz. The switching frequency in MHz can be approximated using Equation 4.
The output filter is composed of a 0.35-µH inductor and 2 × 100-µF capacitors. The inductor is a dual-coil type (Coilcraft SLC7530-820ML) with the coils wired in series. The capacitors used are 100-µF, 6.3-V ceramic types with X5R dielectric.