SLVS847A November   2008  – December 2016 TPS54917

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  Slow Start or Enable (SS/ENA)
      3. 8.3.3  VBIAS Regulator (VBIAS)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Oscillator and PWM Ramp
      6. 8.3.6  Error Amplifier
      7. 8.3.7  PWM Control
      8. 8.3.8  Dead-Time Control and MOSFET Drivers
      9. 8.3.9  Overcurrent Protection
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Power Good (PWRGD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 Standby Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
        2. 9.2.2.2 Input Filter
        3. 9.2.2.3 Feedback Circuit
        4. 9.2.2.4 Operating Frequency
        5. 9.2.2.5 Output Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Estimated Circuit Area
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Developmental Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage, VI SS/ENA, SYNC –0.3 7 V
RT –0.3 6
VSENSE –0.3 4
VIN –0.3 4.5
BOOT –0.3 10
Output voltage, VO VBIAS, PWRGD, COMP –0.6 7 V
PH –0.6 6
PH (transient < 10 ns) –2
Source current, IO PH Internally limited mA
COMP, VBIAS 6
Sink current, IS PH 16 A
COMP 6 mA
SS/ENA, PWRGD 10
Voltage differential (AGND to PGND) ±0.3 V
Operating virtual junction temperature, TJ –40 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage 3 4 V
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS54917 UNIT
RUV (VQFN)
34 PINS
RθJA Junction-to-ambient thermal resistance 27.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.8 °C/W
RθJB Junction-to-board thermal resistance 7.1 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 7.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

TJ = –40°C to 125°C and VI = 3 V to 4 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage 3 4 V
Quiescent current fs = 350 kHz, SYNC ≤ 0.8 V, RT open, PH pin open 9.8 17 mA
fs = 550 kHz, SYNC ≥ 2.5 V, RT open, PH pin open 14 23
Shutdown, SS/ENA = 0 V 1 1.4
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage 2.95 3 V
Stop threshold voltage 2.7 2.8
Hysteresis voltage 0.16 V
Rising and falling edge deglitch(1) 2.5 µs
BIAS VOLTAGE (VBIAS)
VO Output voltage I(VBIAS) = 0 2.7 2.8 2.9 V
Output current(2) 100 µA
CUMULATIVE REFERENCE
Vref Accuracy 0.882 0.891 0.9 V
REGULATION
Line regulation(1) IL = 4.5 A, fs = 350 kHz, TJ = 85°C 0.07% V
IL = 4.5 A, fs = 550 kHz, TJ = 85°C 0.07%
Load regulation(1) IL = 0 A to 9 A, fs = 350 kHz, TJ = 85°C 0.03% A
IL = 0 A to 9 A, fs = 550 kHz, TJ = 85°C 0.03%
OSCILLATOR
Internally set free-running frequency SYNC ≤ 0.8 V, RT open 280 350 420 kHz
SYNC ≥ 2.5 V, RT open 440 550 660
Externally set free-running frequency RT = 100 kΩ (1% resistor to AGND) 460 500 540 kHz
RT = 27 kΩ (1% resistor to AGND) 1480 1600 1720
High-level threshold voltage, SYNC 2.5 V
Low-level threshold voltage, SYNC 0.8 V
Pulse duration, SYNC(1) 50
Frequency range, SYNC 330 1600 kHz
Ramp valley(1) 0.75 V
Ramp amplitude (peak-to-peak)(1) 1 V
Minimum controllable on time 160 ns
Maximum duty cycle 90%
ERROR AMPLIFIER
Error amplifier open loop voltage gain 1 kΩ COMP to AGND(1) 90 110 dB
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND(1) 3 5 MHz
Error amplifier common-mode input voltage range Powered by internal LDO(1) 0 VBIAS V
IIB Input bias current, VSENSE VSENSE = Vref 60 250 nA
VO Output voltage slew rate (symmetric), COMP(1) 1 1.4 V/µs
PWM COMPARATOR
PWM comparator propagation delay time PWM comparator input to PH pin (excluding dead time), 10-mV overdrive(1) 70 85 ns
SLOW START/ENABLE (SS/ENA)
Enable threshold voltage 0.82 1.2 1.4 V
Enable hysteresis voltage(1) 0.03 V
Falling edge deglitch(1) 2.5 µs
Internal slow-start time 2.6 3.35 4.1 ms
Charge current SS/ENA = 0 V 3 5 8 µA
Discharge current SS/ENA = 1.3 V, VI = 1.5 V 1.5 2.3 4 mA
POWER GOOD (PWRGD)
Power good threshold voltage VSENSE falling 90 %Vref
Power good hysteresis voltage(1) 3 %Vref
Power good falling edge deglitch(1) 35 µs
Output saturation voltage I(sink) = 2.5 mA 0.18 0.3 V
Leakage current VI = 5.5 V 1 µA
CURRENT LIMIT
Current limit trip point VI = 3.3 V(1), output shorted 11 15 A
Current limit leading edge blanking time(1) 100 ns
Current limit total response time(1) 200 ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1) 135 150 165 °C
Thermal shutdown hysteresis(1) 10 °C
OUTPUT POWER MOSFETS
rDS(on) Power MOSFET switches VI = 3 V 13.5 26 mΩ
VI = 3.6 V 12.5 24
(1) Specified by design
(2) Static resistive loads only

7.6 Typical Characteristics

TPS54917 drain1_lvs847.gif Figure 1. Drain-Source On-State Resistance
vs Junction Temperature
TPS54917 osc1_lvs847.gif Figure 3. Internally Set Oscillator Frequency
vs Junction Temperature
TPS54917 vref1_lvs847.gif Figure 5. Voltage Reference
vs Junction Temperature
TPS54917 vref2_lvs421.gif Figure 7. Output Voltage Regulation
vs Input Voltage
TPS54917 slow1_lvs847.gif Figure 9. Internal Slow-Start Time vs Junction Temperature
TPS54917 drain2_lvs847.gif Figure 2. Drain-Source On-State Resistance
vs Junction Temperature
TPS54917 osc2_lvs847.gif Figure 4. Externally Set Oscillator Frequency
vs Junction Temperature
TPS54917 power1_lvs847.gif Figure 6. Device Power Losses vs Load Current
TPS54917 oloop1_lvs421.gif Figure 8. Error Amplifier vs Open Loop Response