SNVSBM9B July   2020  – November 2020 TPS54JB20

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3 Control
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering The Device From A 12-V Bus
      4. 7.4.4 Powering The Device From A 3.3-V Bus
      5. 7.4.5 Powering The Device From A Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 Series BOOT Resistor and RC Snubber
        12. 8.2.2.12 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current VIN = 12 V, VEN = 2 V, VFB = VINTREF + 50mV (non-switching), no external bias on VCC pin 910 1007 µA
ISD(VIN) VIN shutdown supply current VIN = 12 V, VEN = 0 V, no external bias on VCC pin 9.5 20 µA
IQ(VCC) VCC quiescent current TJ = 25°C, VIN = 12 V, VEN = 2 V, VFB = VINTREF + 50mV (non-switching), 3.3 V external bias on VCC pin 680 820 µA
ISD(VCC) VCC shutdown current VEN = 0 V, VIN = 0 V, 3.3 V external bias on VCC pin 40 60 µA
UVLO
VINUVLO(rise) VIN UVLO rising threshold VIN rising, VCC = 3.3 V external bias 2.1 2.4 2.7 V
VINUVLO(fall) VIN UVLO falling threshold VIN falling, VCC = 3.3 V external bias 1.55 1.85 2.15 V
ENABLE
VEN(rise) EN voltage rising threshold EN rising, enable switching 1.17 1.22 1.27 V
VEN(fall) EN voltage falling threshold EN falling, disable switching 0.97 1.02 1.07 V
VEN(hyst) EN voltage hysteresis 0.2 V
VEN(LKG) Input leakage current into EN pin VEN = 3.3 V 0.5 5 µA
EN internal pull-down resistance EN pin to AGND. EN floating disables the converter. 6500 kΩ
INTERNAL LDO (VCC PIN)
Internal LDO output voltage VIN = 12 V, IVCC(Load) = 2 mA 2.90 3.02 3.12 V
VCCUVLO(rise) VCC UVLO rising threshold VCC rising 2.80 2.87 2.94 V
VCCUVLO(fall) VCC UVLO falling threshold VCC falling 2.62 2.70 2.77
VCCUVLO(hys) VCC UVLO hysteresis 0.17 V
VCC LDO dropout voltage, 20mA load TJ = 25°C, VIN = 4.0 V, IVCC(Load) = 20 mA, non-switching 1.037 V
VCC LDO short-circuit current limit VIN = 12 V, all temperature 52 105 158 mA
FB Threshold to turn off VCC LDO VCC LDO turn-off is controlled by FB voltage during EN shutdown event 90 146 mV
REFERENCE VOLTAGE
VINTREF Internal voltage reference TJ = 25°C 900 mV
Internal voltage reference range TJ = 0°C to 85°C 896 904 mV
Internal voltage reference range TJ = –40°C to 125°C 891 909 mV
IFB(LKG) Input leakage current into FB pin VFB = VINTREF 1 40 nA
SS/REFIN-to-FB Accuracy TJ = -40°C to 125°C, VSS/REFIN = 0.9 V, VSNS- = AGND, refer to VINTREF –0.6% 0.6%
SWITCHING FREQUENCY
fSW SW switching frequency, FCCM operation TJ = 25°C, VIN = 12 V, VOUT=1.25V, RMODE = 0 Ω to AGND 0.5 0.6 0.7 MHz
TJ = 25°C, VIN = 12 V, VOUT=1.25V, RMODE = 30.1 kΩ to AGND 0.6 0.7 0.8
TJ = 25°C, VIN = 12 V, VOUT=1.25V, RMODE = 60.4 kΩ to AGND 0.70 0.85(3) 1.0
STARTUP
EN to first switching delay, internal LDO The delay from EN goes high to the first SW rising edge with internal LDO configuration. CVCC = 2.2 µF. CSS/REFIN = 220 nF. 0.93 2 ms
EN to first switching delay, external VCC bias The delay from EN goes high to the first SW rising edge with external VCC bias configuration. VCC bias should reach regulation before EN ramp up. CSS/REFIN = 220 nF. 0.55 0.9 ms
tSS Internal fixed Soft-start time VO rising from 0 V to 95% of final setpoint, CSS/REFIN = 1nF 1 1.5 ms
SS/REFIN sourcing current VSS/REFIN = 0 V 36 µA
SS/REFIN sinking current VSS/REFIN = 1 V 12 µA
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, BOOT–SW = 3 V 7.7 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, VCC = 3 V 2.4 mΩ
tON(min) Minimum on-time TJ = 25°C, VCC = Internal LDO 70 85 ns
tOFF(min) Minimum off-time TJ = 25°C, VCC = Internal LDO, HS FET Gate falling to rising 220 ns
BOOT CIRCUIT
IBOOT(LKG) BOOT leakage current TJ = 25°C, VBOOT-SW = 3.3 V 35 50 µA
VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold TJ = 25°C, VIN = 12 V, VBOOT-SW falling 2.0 V
OVERCURRENT PROTECTION
RTRIP TRIP pin resistance range 0 20 kΩ
Current limit clamp Valley current on LS FET, 0-Ω ≤ RTRIP ≤ 5.24-kΩ 19.2 22.9 25 A
KOCL Constant for RTRIP equation 120000 A×Ω
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 5.23kΩ 19.2 22.9 25 A
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 6.04 kΩ 17.5 19.9 22.3 A
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 7.5 kΩ 14.1 16 17.9 A
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 10 kΩ 10.6 12 13.4 A
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 14.7 kΩ 6.7 8.2 9.7 A
IOCL (valley) Current limit threshold Valley current on LS FET, RTRIP = 20 kΩ 4.7 6 7.3 A
KOCL Constant KOCL tolerance  RTRIP = 5.23 kΩ -16.4% 9%
KOCL Constant KOCL tolerance 6.04 kΩ ≤ RTRIP ≤ 10 kΩ -12% 12%
KOCL Constant KOCL tolerance RTRIP = 14.7 kΩ -18% 18%
KOCL Constant KOCL tolerance RTRIP = 20 kΩ -21% 21%
INOCL Negative current limit threshold All VINs –12 –10 –8 A
IZC Zero-cross detection current threshold, open loop VIN = 12 V, VCC = Internal LDO 400 mA
OUTPUT OVP AND UVP
VOVP Output Overvoltage-protection (OVP) threshold voltage 113% 116% 119%
tOVP(delay) Output OVP response delay With 100-mV overdrive 400 ns
VUVP Output Undervoltage-protection (UVP) threshold voltage 77% 80% 83%
tUVP(delay) Output UVP filter delay 68 µs
POWER GOOD
VPGTH PGOOD threshold PGOOD high, FB rising 89% 92.5% 95%
PGOOD low, FB rising 113% 116% 119%
PGOOD low, FB falling 77% 80% 83%
OOB (Out-Of-Bounds) threshold PGOOD high, FB rising 103% 105.5% 108%
IPG PGOOD sink current VPGOOD = 0.4 V, VIN = 12 V, VCC = Internal LDO 17 mA
VPG(low) PGOOD low-level output voltage IPGOOD = 5.5 mA, VIN = 12 V, VCC = Internal LDO 400 mV
tPGDLY(rise) Delay for PGOOD from low to high 1.06 1.33 ms
tPGDLY(fall) Delay for PGOOD from high to low 0.5 5 µs
IPG(LKG) PGOOD leakage current when pulled high TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF 5 µA
PGOOD clamp low-level output voltage VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 100-kΩ resistor 710 850 mV
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 10-kΩ resistor 850 1000 mV
Min VCC for valid PGOOD output VPGOOD ≤ 0.4 V 1.5 V
OUTPUT DISCHARGE
RDischg Output discharge resistance VIN = 12 V, VCC = Internal LDO, VSW = 0.5 V, power conversion disabled 70 Ω
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Temperature rising 150 165 °C
THYST Thermal shutdown hysteresis(1) 30 °C
(1) Specified by design. Not production tested.
(2) Fsw variates with Vout due to D-CAP3 control mode.