SLVSHH9 February 2024 TPS54KC23
PRODUCTION DATA
The device has a power-good (PG or PGOOD) output that goes high to indicate when the converter output is in regulation. The power-good output is an open-drain output and must be pulled up to the VCC pin or an external voltage source (< 5.5V) through a pullup resistor to go high. The recommended power-good pullup resistor value is 1kΩ to 100kΩ.
After the soft-start ramp finishes, the power-good signal becomes high after a 1.3ms internal delay. An internal soft-start done signal goes high when the SS pin voltage reaches VSS(DONE) to indicate the soft-start ramp has finished. If the FB voltage drops to 79% of the VREF voltage or exceeds 116% of the VREF voltage, the power-good signal latches low after a 4µs internal delay. The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.
If an OV event causes the FB voltage to exceed the OV threshold during soft start, but the FB voltage drops below the OV threshold before soft start is completed, the power-good signal is not latched low. Power good pulls low if FB exceeds the OV threshold again or drops below the UV threshold, but does not latch low until after the soft-start ramp finishes. FB exceeding the OV threshold during soft start does however trigger the OV fault response, and the device response to OV typically pulls the output voltage below the UV threshold. The OV fault response is described in Section 6.3.12.
If the input supply fails to power up the device (for example VIN and VCC both stay at zero volts) and this pin is pulled up through an external resistor, the power-good pin clamps low to the low-level specified in the POWER GOOD section in the Electrical Characteristics.