SLVSHH9 February   2024 TPS54KC23

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using External Bias On the VCC Pin
      2. 6.3.2  Enable
      3. 6.3.3  Adjustable Soft Start
      4. 6.3.4  Power Good
      5. 6.3.5  Output Voltage Setting
      6. 6.3.6  Remote Sense
      7. 6.3.7  D-CAP4 Control
      8. 6.3.8  Multifunction Select (MSEL) Pin
      9. 6.3.9  Low-side MOSFET Zero-Crossing
      10. 6.3.10 Current Sense and Positive Overcurrent Protection
      11. 6.3.11 Low-side MOSFET Negative Current Limit
      12. 6.3.12 Overvoltage and Undervoltage Protection
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Powering the Device From a Single Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Output Voltage Setting Point
        2. 7.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 7.2.2.3  Choose the Inductor
        4. 7.2.2.4  Set the Current Limit (ILIM)
        5. 7.2.2.5  Choose the Output Capacitor
        6. 7.2.2.6  RAMP Selection
        7. 7.2.2.7  Choose the Input Capacitors (CIN)
        8. 7.2.2.8  Soft-Start Capacitor (SS Pin)
        9. 7.2.2.9  EN Pin Resistor Divider
        10. 7.2.2.10 VCC Bypass Capacitor
        11. 7.2.2.11 BOOT Capacitor
        12. 7.2.2.12 RC Snubber
        13. 7.2.2.13 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.6 RAMP Selection

To determine the proper ramp selection for this design, the L-C double pole frequency and the maximum L-C double pole frequency must be calculated. The double pole frequency is based on the selected output inductance and output capacitance for this design. Using Equation 30, the L-C double pole frequency for this design is 20kHz. Calculating the maximum L-C double pole frequency then helps guide the user to select one of the four ramp options. Generally, if the L-C double pole calculation lands within the RAMP1 margin, select RAMP1, as this results in the best transient response. Select RAMP2 or RAMP3 if the L-C double pole calculation does not fit within the RAMP1 margin. TI recommends RAMP2 for an increase in phase margin, while TI recommends RAMP3 for higher gain and a faster transient response than RAMP2. If RAMP1, RAMP2, or RAMP3 cannot be selected due to maximum L-C double pole frequency restriction, then choose RAMP4. The maximum L-C double pole frequency can be calculated using Equation 31, where the variable fP(TABLE) equates to the RAMP4 maximum L-C double pole from Table 6-2. This calculation results in 15.4kHz, 19.98kHz, and 26.6 kHz, for RAMP1, RAMP3, and RAMP4 respectively. Because the L-C double pole frequency in this design is 20kHz, which is between RAMP3 and RAMP4, RAMP4 is selected.

Equation 30. f P = 1 2 × π × L O U T × C O U T = 1 2 × π × 0.15   μ H × 412   μ F = 20   k H z
Equation 31. f P ( M A X ) = f P ( T A B L E ) × 1 + V O U T V I N ( t y p ) 2 = 26.5   k H z   × 1 + 0.8   V 12   V 2 = 26.6   k H z

After selecting RAMP4 for this design, connect the MSEL pin to AGND using a 56.2kΩ resistor to set the switching frequency to 800kHz and the ramp option to RAMP4.