SLVSHH9 February   2024 TPS54KC23

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using External Bias On the VCC Pin
      2. 6.3.2  Enable
      3. 6.3.3  Adjustable Soft Start
      4. 6.3.4  Power Good
      5. 6.3.5  Output Voltage Setting
      6. 6.3.6  Remote Sense
      7. 6.3.7  D-CAP4 Control
      8. 6.3.8  Multifunction Select (MSEL) Pin
      9. 6.3.9  Low-side MOSFET Zero-Crossing
      10. 6.3.10 Current Sense and Positive Overcurrent Protection
      11. 6.3.11 Low-side MOSFET Negative Current Limit
      12. 6.3.12 Overvoltage and Undervoltage Protection
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Powering the Device From a Single Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Output Voltage Setting Point
        2. 7.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 7.2.2.3  Choose the Inductor
        4. 7.2.2.4  Set the Current Limit (ILIM)
        5. 7.2.2.5  Choose the Output Capacitor
        6. 7.2.2.6  RAMP Selection
        7. 7.2.2.7  Choose the Input Capacitors (CIN)
        8. 7.2.2.8  Soft-Start Capacitor (SS Pin)
        9. 7.2.2.9  EN Pin Resistor Divider
        10. 7.2.2.10 VCC Bypass Capacitor
        11. 7.2.2.11 BOOT Capacitor
        12. 7.2.2.12 RC Snubber
        13. 7.2.2.13 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Auto-Skip Eco-mode Light Load Operation

If the MSEL resistor value used selects Skip-mode, the device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. Multifunction Select (MSEL) Pin describes the selection in detail.

As the output current decreases from heavy load condition, the inductor current also decreases until the valley of the inductor ripple current touches the zero-crossing threshold (Low-side MOSFET Zero-Crossing). The zero-crossing threshold sets the boundary between the continuous-conduction and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero-crossing threshold is detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM). The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires more time. The transition point to light-load operation IOUT(LL) (for example: the boundary between continuous- and discontinuous-conduction mode) is calculated as shown in Equation 7.

For low output ripple, TI recommends using only ceramic output capacitors for designs that operate in skip-mode.

Equation 7. I O U T ( L L ) = I Z C + 1 2 × V I N - V O U T L × V O U T V I N × f S W