SLUSDX0A September   2020  – August 2021 TPS562211

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Advanced Emulated Current Mode Control
      2. 7.3.2 Mode Selection and PG/SS Pin Function Configuration
      3. 7.3.3 Power Good (PG)
      4. 7.3.4 Soft Start and Pre-Biased Soft Start
      5. 7.3.5 Output Discharge through PG/SS Pin
      6. 7.3.6 Precise Enable and Adjusting Undervoltage Lockout
      7. 7.3.7 Overcurrent Limit and Undervoltage Protection
      8. 7.3.8 Overvoltage Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Operation
      4. 7.4.4 FCCM Operation
      5. 7.4.5 DCM Operation and Eco-Mode Operation
      6. 7.4.6 On-Time Extension for Large Duty Cycle Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Inductor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout Set Point
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Power Good (PG)

This is an optional function configured by the MODE pin.

The device has a built-in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG/SS pin works as an open-drain output that requires a pullup resistor (to any voltage below 5.5 V). A pullup resistor of 10 kΩ is recommended to pull it up to a 5-V voltage. It can sink 0.8 mA of current and maintain its specified logic low level. Once the FB pin voltage is between 92% and 112% of the internal reference voltage (VREF) and after a deglitch time of 112 μs, the PG/SS is high impedance. The PG/SS pin is pulled low after a deglitch time of 48 μs when the FB pin voltage is lower than UVP or greater than OVP threshold, or in events of thermal shutdown, EN shutdown, or UVLO conditions. VIN must remain present for the PG/SS pin to stay low.

If the power-good output is not used when PG function is selected, it is recommended to tie to GND to get better thermal performance.

Table 7-2 Power Good Indicator Logic Table
LOGIC SIGNALS PG LOGIC STATUS
VIN EN TSD VOUT
VIN > UVLO High Not triggered VOUT on target High
VOUT > Target Low
VOUT < Target Low
Triggered ✕ Low
Low ✕ ✕ Low
2.5 V < VIN < UVLO ✕ ✕ ✕ Low
VIN < 2.5 V ✕ ✕ ✕ Undefined