SLVSCB6E November   2013  – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Operation
      2. 8.3.2 PWM Frequency and Adaptive On-Time Control
      3. 8.3.3 VIN and Power VIN Terminals (VIN and PVIN)
      4. 8.3.4 Auto-Skip Eco-mode™ Control
      5. 8.3.5 Soft Start and Pre-Biased Soft Start
      6. 8.3.6 Power Good
      7. 8.3.7 Overcurrent Protection
      8. 8.3.8 UVLO Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation at Light Loads
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 I2C Protocol
      3. 8.5.3 I2C Chip Address Byte
    6. 8.6 Register Maps
      1. 8.6.1 I2C Register Address Byte
      2. 8.6.2 Output Voltage Registers
      3. 8.6.3 CheckSum Bit (VOUT Register Only)
      4. 8.6.4 Control Registers
      5. 8.6.5 Latchoff
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Resistors Selection
            1. 9.2.1.2.1.1 Output Filter Selection
          2. 9.2.1.2.2 Input Capacitor Selection
          3. 9.2.1.2.3 Bootstrap Capacitor Selection
          4. 9.2.1.2.4 VREG5 Capacitor Selection
      2. 9.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
      3. 9.2.3 TPS56C20 12-A Converter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Design Procedure
        3. 9.2.3.3 TPS56C20 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Applications and Implementation

9.1 Application Information

The devices are synchronous step down DC-DC converters rated at different output currents whose output voltage can be dynamically scaled by sending commands over an I2C interface. The section below discusses the design of the external components to complete the power supply design by using a typical application as a reference

9.2 Typical Application

9.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter

TPS56C20 TPS56920 TPS56720 TPS56520 ds_sch_20a_slvscb6.gif Figure 31. Typical Application Schematic – TPS56520, TPS56720 and TPS56920

9.2.1.1 Design Requirements

To begin the design process, the user must know a few application parameters:

  • Input voltage range
  • Output voltage
  • Output current
  • Output voltage ripple
  • Input voltage ripple

Table 4. Design Example

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4.5V to 17V
Output voltage 1.1V
Transient response, 3A-9A load step ΔVOUT = ±5%
Output voltage ripple 25mV
Input ripple voltage 400mA
Output current rating 12A
Operating Frequency 500kHz

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB terminal. It is recommended to use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.

To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to noise, and the voltage errors from the VFB input current are more noticeable.

Equation 3. TPS56C20 TPS56920 TPS56720 TPS56520 EQ3_vo_SLVSCB6.gif

9.2.1.2.1.1 Output Filter Selection

The output filter used with the TPS56X20 is an LC circuit. This LC filter has double pole at:

Equation 4. TPS56C20 TPS56920 TPS56720 TPS56520 eq3_Fp_lvsb3.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS56X20. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 5.

Table 5. Recommended Component Values

Output Voltage (V) R5 (kΩ) R6 (kΩ) C8 (pF)(1) L1 (µH) C7 (µF)
1 14.7 22 DNP 1.0-2.2 44-100
1.1 18.2 22 DNP 1.0-2.2 44-100
1.2 22 22 DNP 1.0-2.2 44-100
1.5 33 22 DNP 1.0-2.2 44-100
1.8 44.2 22 DNP 1.0-2.2 44-100
(1) Optional

For higher output voltages additional phase boost can be achieved by adding a feed forward capacitor (C6) in parallel with R5.

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 500 kHz for fSW.

Use 500 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS current of Equation 7.

Equation 5. TPS56C20 TPS56920 TPS56720 TPS56520 eq4_Ilpp_lvsbv4.gif
Equation 6. TPS56C20 TPS56920 TPS56720 TPS56520 eq5_Ilpeak_lvsbv4.gif
Equation 7. TPS56C20 TPS56920 TPS56720 TPS56520 eq6_Ilorms_lvsbv4.gif

The capacitor value and ESR determines the amount of output voltage ripple. The TPS56X20 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 44µF to 100µF. Use Equation 8 to determine the required RMS current rating for the output capacitor.

Equation 8. TPS56C20 TPS56920 TPS56720 TPS56520 eq8_lvsaAG1.gif

9.2.1.2.2 Input Capacitor Selection

The TPS56X20 requires an input decoupling capacitor and a bulk capacitor depending on the application. A ceramic capacitor of 20µF or above is recommended for the decoupling capacitors from PVIN to PGND. Additionally, a 4.7 µF ceramic capacitor from VIN to GND is also recommended. The capacitors voltage rating needs to be greater than the maximum input voltage.

9.2.1.2.3 Bootstrap Capacitor Selection

The 0.1 µF ceramic capacitors must be connected between the VBST to SW terminals for proper operation. It is recommended to use ceramic capacitors with a dielectric of X5R or better.

9.2.1.2.4 VREG5 Capacitor Selection

For the TPS56920/720/520, a 2.2 µF ceramic capacitor must be connected between the VREG5 to GND terminals for proper operation.

9.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves

VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.

TPS56C20 TPS56920 TPS56720 TPS56520 C029_SLVSCB6.png
Figure 32. TPS56520 Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C031_SLVSCB6.png
Figure 34. TPS56520 Load Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C033_SLVSCB6.png
Figure 36. TPS56520 Line Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C035_SLVSCB6.png
Figure 38. TPS56720 Eco-mode™ Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C037_SLVSCB6.png
Figure 40. TPS56720 Load Regulation with Eco-mode™
TPS56C20 TPS56920 TPS56720 TPS56520 C039_SLVSCB6.png
Figure 42. TPS56920 Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C041_SLVSCB6.png
Figure 44. TPS56920 Load Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C043_SLVSCB6.png
Figure 46. TPS56920 Line Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 vi_rip_SLVSCB6.gif
Figure 48. TPS56920 Input Voltage Ripple
TPS56C20 TPS56920 TPS56720 TPS56520 start_Vin_SLVSCB6.gif
Figure 50. TPS56920 Start Up Relative to VIN
TPS56C20 TPS56920 TPS56720 TPS56520 C030_SLVSCB6.png
Figure 33. TPS56520 Eco-mode™ Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C032_SLVSCB6.png
Figure 35. TPS56520 Load Regulation with Eco-mode™
TPS56C20 TPS56920 TPS56720 TPS56520 C034_SLVSCB6.png
Figure 37. TPS56720 Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C036_SLVSCB6.png
Figure 39. TPS56720 Load Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C038_SLVSCB6.png
Figure 41. TPS56720 Line Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C040_SLVSCB6.png
Figure 43. TPS56920 Eco-mode™ Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C042_SLVSCB6.png
Figure 45. TPS56520 Load Regulation with Eco-mode™
TPS56C20 TPS56920 TPS56720 TPS56520 transient_SLVSCB6.gif
Figure 47. TPS56920 Transient Response
TPS56C20 TPS56920 TPS56720 TPS56520 vo_rip1_SLVSCB6.gif
Figure 49. TPS56920 Output Voltage Ripple

9.2.3 TPS56C20 12-A Converter

TPS56C20 TPS56920 TPS56720 TPS56520 ds_sch_24a_slvscb6.gif Figure 51. Typical Schematic – TPS56C20

9.2.3.1 Design Requirements

To begin the design process, the user must know a few application parameters:

  • Input voltage range
  • Output voltage
  • Output current
  • Output voltage ripple
  • Input voltage ripple

9.2.3.2 Design Procedure

Follow the design procedure for the TPS56X20 converter listed above. For the TPS56C20, a 3.3 µF ceramic capacitor must be connected between the VREG5 to GND terminals for proper operation. Do not load the VREG5 terminal with any other load. It is recommended to use a ceramic capacitor with a dielectric of X5R or better.

9.2.3.3 TPS56C20 Application Performance Curves

VIN = 12 V, VOUT = 1.0 V, Ta = 25 °C, unless otherwise specified.

TPS56C20 TPS56920 TPS56720 TPS56520 C044_SLVSCB6.png
Figure 52. TPS56C20 Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C046_SLVSCB6.png
Figure 54. TPS56C20 Load Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C048_SLVSCB6.png
Figure 56. TPS56C20 Line Regulation
TPS56C20 TPS56920 TPS56720 TPS56520 C045_SLVSCB6.png
Figure 53. TPS56C20 Eco-mode™ Efficiency
TPS56C20 TPS56920 TPS56720 TPS56520 C047_SLVSCB6.png
Figure 55. TPS56C20 Load Regulation with Eco-mode™