8.3.1 PWM Operation

The main control loop of the TPS56X20 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal timer expires. This timer is set by the converter’s input voltage, VIN, and the output voltage, VOUT, to maintain a pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.

8.3.2 PWM Frequency and Adaptive On-Time Control

TPS56X20 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS56X20 runs with a pseudo-constant frequency of 500 kHz by using the input voltage and output voltage to set the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VO/PVIN, the frequency is constant.

8.3.3 VIN and Power VIN Terminals (VIN and PVIN)

The device allows for a variety of applications by using the VIN and PVIN terminals together or separately. The VIN terminal voltage supplies the internal control circuits of the device. The PVIN terminal voltage provides the input voltage to the power converter system. The input voltage for VIN and PVIN can range from 4.5V to 17V.

8.3.4 Auto-Skip Eco-mode™ Control

The TPS56X20 is designed with Auto-Skip Eco-mode™ to increase light load efficiency.

8.3.5 Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN terminal becomes high, 6-µA current begins charging the capacitor which is connected from the SS terminal to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.6 V and SS terminal source current is 6µA.

Equation 1.

The TPS56X20 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage, VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOUT) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. When pre-biased conditions exist, it is recommended to disable the device by pulling the EN terminal to ground.

8.3.6 Power Good

The power-good function is activated after soft start has finished. The PGOOD output is an open drain output. When the output voltage is between 85% and 110% of the target value, internal comparator detect power good state and the power good signal becomes high. If the output voltage is lower than 80% or greater than 115% of the target value, the power good signal becomes low.

8.3.7 Overcurrent Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW terminal and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. The TPS56X20 constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of overcurrent protection. The peak current is the average load current plus one half of the peak-to-peak inductor current. The valley current is the average load current minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. When the output voltage becomes lower than 60% of the target voltage, the UVP comparator detects it. Depending on the values of Hiccup Mode bit and UVP Latchoff Mode bit in the Control A and Control B registers, the device may enter Hiccup Mode or Latchoff Mode or keep running under cycle-by-cycle current limiting.

The TPS56X20 also implements reverse overcurrent protection. When reverse overcurrent protection is triggered, the high-side MOSFET turns on for the preset on-time and then the low-side MOSFET turns on to monitor the switch valley current. The high-side MOSFET turns on again if either VFB pin voltage drops below reference voltage, or the reverse switch current hits the reverse current trip point.

8.3.8 UVLO Protection

Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 terminal. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS56X20 is shut off. This protection is non-latching.

8.4.1 Operation at Light Loads

The TPS56x20 works in Auto-Skip Eco-mode^TM at light load to boost the efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the where its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is kept same as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with smaller load current to the level of the nominal output voltage. The transition point to the light load operation I_O(LL) current can be estimated with Equation 2 with 500kHz used as ƒsw.

Equation 2.

8.5.1 I²C Interface

The TPS56X20 implements a subset of the Phillips I²C specification Ver. 1.1. The TPS56X20 is a Slave-Only (it never becomes a Master, and so never pulls down the SCL terminal on the I²C bus). An I²C transaction consists of either writing a data byte to one of the TPS56X20’s internal registers which requires a 3-byte transaction or reading back one byte from a register which requires a 4-byte transaction. The protocols follow the System Management Bus (SMBUS) Specification Ver. 2.0 Write Byte and Read Byte protocols. This spec is available on the Internet for further reading, but the subset implemented in TPS56X20 is described below.

Long-form address modes, multi-byte data transfers and Packet Error Code (PEC) protocols are not supported in this implementation, though a Check Sum bit unique to the TPS56X20 is implemented and described below. The SMBUS Send Byte protocol (the 2-byte protocol used in TPS56921) is not implemented on TPS56X20.

The I²C interface terminals are composed of the SDA (Data) and SCL (Clock) terminals, and the A0 and A1 terminals to set up the chip’s address. SDA and SCL are designed to be used with pullup resistors to 3.3V. A0 and A1 are designed to be either grounded (logic LOW) or left open (logic HIGH) and should not tie to a high voltage.

8.5.2 I²C Protocol

Input voltage – Logic levels for I²C SDA and SCL terminals are not fixed. For the TPS56X20, a logic “0” (LOW) should be 0V and a logic “1” (HIGH) can be any voltage between 1.8V and 3.3V. Logic HIGH is generated by external pullup resistors (see next paragraph).

Output voltage – the I²C bus has external pullup resistors, one for SCL and one for SDA. These pull up to a voltage called VDD which must lie between 1.8V and 3.3V. The outputs are pulled down to their logic LOW levels by open-drain outputs and pulled up to their logic HIGH levels by these external pullups. The pullups must be selected so that the current into any chip when pulled LOW by that chip’s open drain output (=VDD/RPULLUP) is less than 3.3mA.

Data format – One clock pulse on the SCL clock line is generated for each bit of data to be transferred. The data on the SDA line must be stable during the HIGH period of the SCL clock line. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

START and STOP conditions – A HIGH to LOW transition on the SDA line while the SCL line is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while the SCL line is HIGH defines a STOP condition. START and STOP conditions are always generated by the Master. The bus is considered to be BUSY after the condition. It is considered to be free again after a minimum of 4.7µS after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. START and repeated START are functionally identical.

Every byte of data out on the SDA line is 8 bits long. 9 clocks occur for each byte (the additional clock being for an ACK signal put onto the bus by the TPS56X20 pulling down on the bus to acknowledge receipt of the data). In the following diagrams, shaded blocks indicate SDA data generated by the TPS56X20 being sent to the Master I²C controller, while white blocks indicate SDA data generated by the Master being received by the TPS56X20. The Master always generates the SCL signal.

Sending data to the TPS56X20 is accomplished using the following 3-byte sequence, referred to as a Write Byte transaction as follows:

Figure 29. A complete Write Byte transfer, adapted from SMBUS spec

Reading back data from the TPS56X20 is accomplished using the following 4-byte sequence, referred to as a Read Byte transaction:

Figure 30. A complete Read Byte transfer, adapted from SMBUS spec

On the TPS56X20, the I2C bus is inactive until:

1. Both SDA and SCL have been at a logic high simultaneously to prevent power sequencing issues
2. VREG5 is in regulation.

Control registers should not be written to during the Soft Start time, but can be written before VOUT is enabled or after the PGOOD terminal or status register go high, indicating that soft start is complete.

Until a VOUT command has been accepted, the TPS56X20’s output voltage will be determined by the external resistor divider feedback to the VFB terminals, the condition of the EN terminals, and the capacitance on the SS terminals.

When the TPS56X20 receives a Chip Address code it recognizes to be its own, it will respond by sending an ACK (pulling down on the SDA bus during the next clock on the SCL bus). If the address is not recognized, the TPS56X20 assumes that the I²C message is intended for another chip on the bus, and it takes no action. It will disregard data sent thereafter until the next START is begun.

If, after recognizing its Chip Address, the TPS56X20 receives a valid Register Address, it will send an ACK and prepare to receive a Data Byte to be sent to that Register.

If a valid Data Byte is then received, it will send an ACK and will set the output voltage to the desired value. If the byte is deemed invalid, ACK will not be sent and the Master will need to retry by sending a STOP sequence followed by a new START sequence and an initiating resend of the entire address/data packet. When sending data to the Output Voltage register, the output voltage will only change upon receipt of a valid data byte.

8.5.3 I²C Chip Address Byte

The 7-bit address of the TPS56X20 can be any number between 34h (0110100) and 37h (0110111). The 5 MSB’s are set internally and the 2 LSB’s are customer-selectable via the A1 and A0 terminals, allowing up to 4 TPS56X20’s to be controlled on the same I2C bus. When the Master is sending the address as an 8-bit value, the 7-bit address should be sent followed by a trailing 0 to indicate this is a WRITE operation. A0 and A1 must be floated for logic 1. Do not tie them to external voltage source. The following codes assume this trailing zero.

8.6.1 I²C Register Address Byte

The TPS56X20 contains four customer-accessible registers. Register 0 is the Output Voltage register. Registers 8 and 9 set several operating features for the regulator. The lower 3 bits of Register 9 sets the current limit for the high-current, etc. Register 24 provides the status of the regulator. The register map is as follows:

8.6.2 Output Voltage Registers

The lower 7 bits of the Output Voltage Register controls the VOUT of the TPS56X20. These bits are the 7-bit selector for one of the output voltages.

As previously mentioned, when the IC powers up, the startup and output voltage regulation conditions are set by the external resistor divider feedback to the VFB terminal, the condition of the EN terminal, and the capacitance on the SS terminal.

Bringing the EN terminal high (or setting the Enable bit in Control register 9 high) begins a soft-start ramp on the regulator.

After applying VIN, VREG5 will come into regulation and the I2C interface will active. The user can activate soft start and VOUT by bring the EN terminal high or programming the Enable bit in Control Register 9.

By default, the part will regulate VOUT using the external feedback resistors connected to the VFB terminal. The user can then program VOUT by writing any VOUT code. Alternatively, if the EN terminal is low, soft start and VOUT can be enabled by writing the desired VOUT code and programming the Enable bit to a one.

8.6.3 CheckSum Bit (VOUT Register Only)

The CheckSum bit should be set by the Master controller to be the exclusive-NOR of the D[6:0] bits (odd parity). This will be used by the TPS56X20 to check that a valid data byte was received. If CheckSum is not equal to the exclusive-NOR of these bits, the TPS56X20 assumes that an error occurred during the data transmission, and it will not send an ACK bit, nor will it reset the VOUT to the received code (or, if the Control register, will not reset the register contents as requested). The Master should try again to send the data. When reading back the VOUT register, the parity bit is also sent back.

8.6.4 Control Registers

There are 4 control registers: Registers 0, 8, 9 and 24.

Enable: This bit can be used to enable the regulator just like setting the EN terminal high. The EN terminal has priority (if EN=high, the Enable bit does nothing, the chip is already enabled). This allows the customer to tie EN to GND externally or leave the EN terminal floating (the terminal is pulled low internally) and subsequently enable the regulator by I²C software control.

DAC Settle [1:0]: When a new VOUT voltage is selected, this happens by setting an internal DAC to a new internal VREF voltage. If this happens instantly, the regulator loop will be thrown out of regulation and the DCAP2 loop must respond to bring the VOUT back into regulation at its new chosen value. This can cause VOUT overshoots (or undershoots) or head to high transient input currents. Therefore, an analog filter on the DAC output causes this internal VREF to change more slowly. The DAC Settle[1:0] bits change the filter time constant as follows:

The power-up default value of the DAC Settle[1:0] bits is 11.

Internal Mode: This bit can be interrogated to discover whether the chip is running in EXT Mode (using external resistor dividers to VFB terminal to set the output voltage) or INT Mode (using codes set in Output Voltage register to set the output voltage). Further, it can be set by the user to force either Internal or External mode. Writing a valid value to a VOUT register always sets External to 1 on the corresponding regulator.

In default, the TPS56X20 will start up into external mode and the output voltage is set by VFB with divider resistors. If starting up into internal VID mode is desired, the input voltage should be applied first, write Internal Mode bit to "1" the next, then enable the device by EN terminal or EN bit.

Current Limit [2:0]: Set the low-side valley current limit threshold for the regulator. Power-up default setting is [111].

PGOOD Delay [1:0]: Especially for low load currents, large jumps in the I²C-controlled VOUT setting may have a long settling time compared to the UV/OV thresholds. If this happens, it will cause the PGOOD signal to temporarily indicate a fault condition. If this is not the desired behavior, it is possible to “blank” the PGOOD being pulled down for some number of µS according to the table below.

On power-up, the delay defaults to 26.4 µS. The user can reset the blanking time using these codes at any time without affecting any other device behavior.

8.6.5 Latchoff

Latchoff turns the output voltage off in the event of an overvoltage or undervoltage condition. V_OUT will not be enabled again until the EN terminal or EN bit is cycled. By default Latchoff Mode is disabled, but overvoltage protection (OVP) and undervoltage protection (UVP) Latchoff Modes can be enabled by setting the OVP and UVP Latchoff Mode Off bits to zero. Power cycling Vin will reset these bits to their default values. If either Latchoff Mode is enabled, Hiccup Mode On should be disabled.