SLVSCV3B March   2015  – June 2015 TPS566250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Operation
      2. 8.3.2 PWM Frequency and Adaptive On-Time Control
      3. 8.3.3 Soft Start and Pre-Biased Soft Start
      4. 8.3.4 Overcurrent Protection
      5. 8.3.5 UVLO Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Auto-Skip Eco-mode™ Control
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 I2C Protocol
        1. 8.5.2.1 Input Voltage
        2. 8.5.2.2 Output Voltage
        3. 8.5.2.3 Data Format
        4. 8.5.2.4 START and STOP Conditions
      3. 8.5.3 I2C Chip Address Byte
    6. 8.6 Register Maps
      1. 8.6.1 I2C Register Address Byte
        1. 8.6.1.1 Output Voltage Register (offset = 00000000) [reset = 0h]
        2. 8.6.1.2 Power Good State Register (offset = 00011000) [reset = 18h]
      2. 8.6.2 CheckSum Bit
      3. 8.6.3 Output Voltage Registers
      4. 8.6.4 Summary of Default Control Bits
        1. 8.6.4.1 DAC Settle
        2. 8.6.4.2 Operation During VID Transition
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Resistors Selection
        2. 9.2.2.2 Output Filter Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Bootstrap Capacitor Selection
      3. 9.2.3 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Third-Party Products Disclaimer
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Thermal Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPS566250 is a synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™ control reduces the required output capacitance required to meet a specific level of performance. The output voltage of the device can be set by either FB with divider resistors and I2C compatible interface.

8.2 Functional Block Diagram

TPS566250 fbd_slvscv3.gif

8.3 Feature Description

8.3.1 PWM Operation

The main control loop of the TPS566250 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal timer expires. This timer is set by the converter’s input voltage, VIN, and the output voltage, VOUT, to maintain a pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.

8.3.2 PWM Frequency and Adaptive On-Time Control

TPS566250 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The device runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the switching frequency is constant.

8.3.3 Soft Start and Pre-Biased Soft Start

The TPS566250 has an internal 1 ms soft-start. When the EN pin becomes high, internal soft-start function begins ramping up the reference voltage to the PWM comparator. The device contains a unique circuit to prevent sinking current from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage FB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from output pre-biased startup to normal mode operation.

8.3.4 Overcurrent Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOUT. The device constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time. If the measured voltage is above the voltage proportional to the current limit, the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the overcurrent condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the higher value.

There are some important considerations for valley overcurrent protection. The average load current is half the peak-to-peak inductor current plus the valley overcurrent threshold during current limit. The output voltage falls as the demanded load current exceeds the current limit. When the FB voltage becomes lower than 65% of the target voltage, the UVP comparator detects it and the Hiccup sequence is initiated. After 10 µs detecting the UVP voltage, device shuts down and re-starts after the hiccup time.

When the over current condition is removed, the output voltage returns to the regulated value.

8.3.5 UVLO Protection

Undervoltage lock out protection (UVLO) monitors the voltage of the VIN terminal. When the VIN voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.

8.3.6 Thermal Shutdown

TPS566250 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), the device is shut off. This is non-latch protection.

8.4 Device Functional Modes

8.4.1 Auto-Skip Eco-mode™ Control

The TPS566250 is designed with Advanced Eco-mode™ to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the where its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is lowered to reduce the output voltage ripple. The transition point to the light load operation IO(LL) current can be estimated with Equation 1 with 650 kHz used as fSW.

Equation 1. TPS566250 eq_1_slvscv3.gif

8.5 Programming

8.5.1 I2C Interface

The TPS566250 implements a subset of the Phillips I2C specification Ver. 1.1. The TPS566250 is a Slave-Only (it never becomes a Master, and so never pulls down the SCL pin on the I2C bus). An I2C transaction consists of either writing a data byte to one of the device internal registers which requires a 3-byte transaction or reading back one byte from a register which requires a 4-byte transaction. The protocols follow the System Management Bus (SMBUS) Specification Ver. 2.0 Write Byte and Read Byte protocols. This spec is available on the Internet for further reading, but the subset implemented in TPS566250 is described as:

  • Long-form address modes, multi-byte data transfers and Packet Error Code (PEC) protocols are not supported in this implementation, though a unique to the TPS566250.
  • The I2C interface pins are composed of the SDA (Data) and SCL (Clock) pins. SDA and SCL are designed to be used with pullup resistors to 3.3 V.

8.5.2 I2C Protocol

8.5.2.1 Input Voltage

Logic levels for I2C SDA and SCL pins are not fixed. For the TPS566250, a logic “0” (LOW) should be 0 V and a logic “1” (HIGH) can be any voltage between 2.5 V and 3.3 V. Logic HIGH is generated by external pullup resistors (see Output Voltage).

8.5.2.2 Output Voltage

the I2C bus has external pullup resistors, one for SCL and one for SDA. These pull up to a voltage called VDD which must lie between 2.5 V and 3.3 V. The outputs are pulled down to their logic LOW levels by open-drain outputs and pulled up to their logic HIGH levels by these external pullups. The pullups must be selected so that the current into any chip when pulled LOW by that chip’s open drain output (=VDD/RPULLUP) is less than 3 mA.

8.5.2.3 Data Format

One clock pulse on the SCL clock line is generated for each bit of data to be transferred. The data on the SDA line must be stable during the HIGH period of the SCL clock line. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

8.5.2.4 START and STOP Conditions

A HIGH to LOW transition on the SDA line while the SCL line is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while the SCL line is HIGH defines a STOP condition. START and STOP conditions are always generated by the Master. The bus is considered to be BUSY after the condition. It is considered to be free again after a minimum of 4.7 µS after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. START and repeated START are functionally identical.

Every byte of data out on the SDA line is 8 bits long. 9 clocks occur for each byte (the additional clock being for an ACK signal put onto the bus by the device pulling down on the bus to acknowledge receipt of the data). In the Figure 13 and Figure 14, shaded blocks indicate SDA data generated by the device being sent to the Master I2C controller, while white blocks indicate SDA data generated by the Master being received by the device. The Master always generates the SCL signal.

Sending data to the TPS566250 is accomplished using the following 3-byte sequence, referred to as a Write Byte transaction:

TPS566250 write_byte_transfer_SLVSCB6.gifFigure 13. A Complete Write Byte Transfer, Adapted From SMBUS Spec

Reading back data from the TPS566250 is accomplished using the following 4-byte sequence, referred to as a Read Byte transaction:

TPS566250 read_byte_transfer_SLVSCB6.gifFigure 14. A Complete Read Byte Transfer, Adapted From SMBUS Spec

On the TPS566250, the I2C bus is inactive until:

  1. Both SDA and SCL have been at a logic high simultaneously to prevent power sequencing issues.
  2. VOUT is in regulation.

Control registers can be written after soft start is complete (1.7 times soft start time).

Until a VOUT command has been accepted, the device output voltage is determined by the external resistor divider feedback to the FB pin, the initial FB voltage (typically 0.6 V), and the condition of the EN pin.

When the device receives a Chip Address code it recognizes to be its own, it responds by sending an ACK (pulling down on the SDA bus during the next clock on the SCL bus). If the address is not recognized, the device assumes that the I2C message is intended for another chip on the bus, and it takes no action. It disregards data sent thereafter until the next START is begun.

If, after recognizing its Chip Address, the TPS566250 receives a valid Register Address, it sends an ACK and prepare to receive a Data Byte to be sent to that Register.

If a valid Data Byte is then received, it sends an ACK and sets the output voltage to the desired value. It is recommended to readback to verify the output voltage code. When sending data to the Output Voltage register, the output voltage only changes upon receipt of a valid data byte.

8.5.3 I2C Chip Address Byte

The 7-bit address of the TPS566250 is set at 31h in hex notation (0110001 in binary notation) internally. When the Master is sending the address as an 8-bit value, the 7-bit address should be sent followed by a trailing 0 to indicate this is a WRITE operation.

8.6 Register Maps

8.6.1 I2C Register Address Byte

The TPS566250 contains 2 customer-accessible registers. Register 0d (0h) is the output voltage register. Register 24d (18h) is the power good register

8.6.1.1 Output Voltage Register (offset = 00000000) [reset = 0h]

Register 0d (0h) is the Output Voltage resister.

Figure 15. Output Voltage Register
7 6 5 4 3 2 1 0
Odd Parity VOUT
R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1. Output Voltage Register

Bit Field Type Reset Description
7 Odd Parity R/W 0h See CheckSum Bit
6:0 VOUT R/W 0h See Table 3

8.6.1.2 Power Good State Register (offset = 00011000) [reset = 18h]

Register 24d (18h) provides the power good state

Figure 16. Power Good State Register
7 6 5 4 3 2 1 0
TI only PGOOD
R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2. Power Good Register

Bit Field Type Reset Description
7:1 TI only R 0h TI only
0 PGOOD R 18h 1 = FB voltage within PGOOD threshold limits
0 = FB Voltage outside PGOOD threshold limits

8.6.2 CheckSum Bit

The CheckSum bit should be set by the Master controller to be the exclusive-OR of the D[6:0] bits (odd parity). This is used by the TPS566250 to check that a valid data byte was received. If CheckSum is not equal to the exclusive-OR of these bits, the TPS566250 assumes that an error occurred during the data transmission, nor does not reset the VOUT to the received code (or, if the Control register does not reset the register contents as requested). The Master should try again to send the data.

8.6.3 Output Voltage Registers

The lower 7 bits of the Output Voltage Register controls the VOUT of the device. These bits are the 7-bit selector for one of the output voltages. The default output voltage is 1.1 V, that is 50d (32h)

When the IC powers up, the startup and output voltage regulation conditions are set by the external resistor divider feedback to the FB pin, the initial FB voltage and the condition of the EN pin. Bringing the EN pin high begins a soft-start ramp on the regulator.

After applying VIN, VOUT comes into regulation and the I2C interface actives.

By default, the device regulates VOUT using the external feedback resistors connected to the FB pin and the initial FB voltage. The user can then program VOUT by writing any VOUT code.

Table 3. Ideal VOUT vs VOUT [6:0] Code
(Upper/lower Feedback Resistors: 1.37 kΩ / 1.65 kΩ (1)(2)

Code Binary VOUT Code Binary VOUT Code Binary VOUT Code Binary VOUT
0 0000000 0.60 32 0100000 0.92 64 1000000 1.24 96 1100000 1.56
1 0000001 0.61 33 0100001 0.93 65 1000001 1.25 97 1100001 1.57
2 0000010 0.62 34 0100010 0.94 66 1000010 1.26 98 1100010 1.58
3 0000011 0.63 35 0100011 0.95 67 1000011 1.27 99 1100011 1.59
4 0000100 0.64 36 0100100 0.96 68 1000100 1.28 100 1100100 1.60
5 0000101 0.65 37 0100101 0.97 69 1000101 1.29 101 1100101 1.61
6 0000110 0.66 38 0100110 0.98 70 1000110 1.30 102 1100110 1.62
7 0000111 0.67 39 0100111 0.99 71 1000111 1.31 103 1100111 1.63
8 0001000 0.68 40 0101000 1.00 72 1001000 1.32 104 1101000 1.64
9 0001001 0.69 41 0101001 1.01 73 1001001 1.33 105 1101001 1.65
10 0001010 0.70 42 0101010 1.02 74 1001010 1.34 106 1101010 1.66
11 0001011 0.71 43 0101011 1.03 75 1001011 1.35 107 1101011 1.67
12 0001100 0.72 44 0101100 1.04 76 1001100 1.36 108 1101100 1.68
13 0001101 0.73 45 0101101 1.05 77 1001101 1.37 109 1101101 1.69
14 0001110 0.74 46 0101110 1.06 78 1001110 1.38 110 1101110 1.70
15 0001111 0.75 47 0101111 1.07 79 1001111 1.39 111 1101111 1.71
16 0010000 0.76 48 0110000 1.08 80 1010000 1.40 112 1110000 1.72
17 0010001 0.77 49 0110001 1.09 81 1010001 1.41 113 1110001 1.73
18 0010010 0.78 50 0110010 1.10 82 1010010 1.42 114 1110010 1.74
19 0010011 0.79 51 0110011 1.11 83 1010011 1.43 115 1110011 1.75
20 0010100 0.80 52 0110100 1.12 84 1010100 1.44 116 1110100 1.76
21 0010101 0.81 53 0110101 1.13 85 1010101 1.45 117 1110101 1.77
22 0010110 0.82 54 0110110 1.14 86 1010110 1.46 118 1110110 1.78
23 0010111 0.83 55 0110111 1.15 87 1010111 1.47 119 1110111 1.79
24 0011000 0.84 56 0111000 1.16 88 1011000 1.48 120 1111000 1.80
25 0011001 0.85 57 0111001 1.17 89 1011001 1.49 121 1111001 1.81
26 0011010 0.86 58 0111010 1.18 90 1011010 1.50 122 1111010 1.82
27 0011011 0.87 59 0111011 1.19 91 1011011 1.51 123 1111011 1.83
28 0011100 0.88 60 0111100 1.20 92 1011100 1.52 124 1111100 1.84
29 0011101 0.89 61 0111101 1.21 93 1011101 1.53 125 1111101 1.85
30 0011110 0.90 62 0111110 1.22 94 1011110 1.54 126 1111110 1.86
31 0011111 0.91 63 0111111 1.23 95 1011111 1.55 127 1111111 1.87
(1) 10-mV output voltage steps can be applied to 1.1-V output voltage setting only.
(2) For other default voltage setting, the output voltage step are shown in Equation 2.
Equation 2. Output Voltage Step = 10 x Target Output Voltage/1.1 mV

8.6.4 Summary of Default Control Bits

8.6.4.1 DAC Settle

When a new VOUT voltage is selected, this happens by setting an internal DAC to a new internal VREF voltage. If this happens instantly, the regulator loop is thrown out of regulation and the DCAP2 loop must respond to bring the VOUT back into regulation at its new chosen value. To reduce VOUT overshoots (or undershoots) or high transient input currents due to the internal VREF change, There is an analog filter on the DAC output. The filter is set at 20 µs constant.

8.6.4.2 Operation During VID Transition

The device temporarily goes into forced CCM mode during VID transitions for approximately 100 µs. This helps discharge VOUT during a step down when there is a light load present. The Power Good is masked for approximately 100 µs to prevent a power good flag during the transition.

CONTROL BIT(S) DEFAULT FUNCTION
VOUT[7:0] 0110010
(32h)		 VOUT code, 7 bits VOUT[6:0] + odd parity checksum bit at VOUT[7].
Writing a valid code to this register also sets VID Mode. Sending an invalid code (checksum incorrect) to this register does not change register contents or set Internal/Enable bits.