11.1 Layout Guidelines

1. Keep the input switching current loop as small as possible. And avoid the input switching current through thermal Pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback terminal of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to GND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Kelvin connections should be brought from the output to the feedback terminal of the device.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. Input capacitors should be placed as near as possible to the device.
15. The topside and the bottom side of the PCB should be filled with as much ground plane as possible that has an uninterrupted heat flow path. The ground plane should be made as large as possible. The PVIN cap should connect to PGND and the VIN cap should connect to GND.  

11.2 Layout Example

Figure 57. TPS56X20 Board Layout