SLVSGI6D october   2022  – september 2023 TPS61033 , TPS610333

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout
      2. 8.3.2  Enable and Soft Start
      3. 8.3.3  Setting the Output Voltage
      4. 8.3.4  Current Limit Operation
      5. 8.3.5  Pass-Through Operation
      6. 8.3.6  Power Good Indicator
      7. 8.3.7  Implement Output Discharge by PG function
      8. 8.3.8  Overvoltage Protection
      9. 8.3.9  Output Short-to-Ground Protection
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Mode
      2. 8.4.2 Power-Save Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting the Output Voltage
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 3.6 V and VOUT = 5.0 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 1.8 5.5 V
VIN_UVLO Under-voltage lockout threshold VIN rising 1.7 1.79 V
VIN falling 1.6 V
VIN_HYS VIN UVLO hysteresis 65 mV
IQ Quiescent current into VIN pin IC enabled, No load, No switching VIN = 1.8 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C 13 20 25 µA
Quiescent current into VOUT pin IC enabled, No load, No switching VOUT = 2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C 5.3 9 µA
ISD Shutdown current into VIN and SW pin IC disabled, VIN = VSW = 3.6 V, TJ = 25°C 0.1 0.2 µA
OUTPUT
VOUT Output voltage setting range 2.2 5.5 V
VOUT (fixed 5V) Fixed output voltage FB connected to VIN
VIN < VOUT, PWM mode		 4.93 5 5.07 V
VREF Reference voltage at the FB pin PWM mode 591 600 609 mV
VREF Reference voltage at the FB pin PFM mode 606 mV
VOVP Output over-voltage protection threshold VOUT rising 5.5 5.75 6.0 V
VOVP_HYS Over-voltage protection hysteresis 0.11 V
IFB_LKG Leakage current at FB pin TJ = 25°C 4 25 nA
IFB_LKG Leakage current at FB pin TJ = 125°C 5 30 nA
IVOUT_LKG Leakage current into VOUT pin IC disabled, VIN = 0 V, VSW = 0 V, VOUT = 5.5 V, TJ = 25°C 0.2 0.5 µA
tss Soft startup time Internal SS ramp time 0.86 ms
POWER SWITCH
RDS(on) High-side MOSFET on resistance VOUT = 5.0 V 46 mΩ
RDS(on) Low-side MOSFET on resistance VOUT = 5.0 V 25 mΩ
fSW Switching frequency VIN = 3.6 V, VOUT = 5.0 V, PWM mode 2.0 2.4 2.8 MHz
tON_min Minimum on time 20 48 65 ns
tOFF_min Minimum off time 35 70 ns
ILIM_SW Valley current limit VIN = 3.6 V, VOUT = 5.0 V TPS61033 4.7 5.5 6.1 A
ILIM_SW Valley current limit VIN = 3.6 V, VOUT = 5.0 V TPS610333 1.55 1.85 2.25 A
IREVERSE Reverse current limit (MODE=1) VIN = 3.6 V, VOUT = 5.0 V; MODE = 1 -1.4 A
ILIM_CHG Pre-charge current VIN = 1.8 - 5.5 V, VOUT < 0.4 V 330 mA
ILIM_CHG_max Maximum pre-charge current VIN = 2.4 V, VOUT > 0.4 V ; TPS610333 800 1100 mA
LOGIC INTERFACE
VEN_H EN logic high threshold VIN > 1.8 V or VOUT > 2.2 V 1.2 V
VEN_L EN logic low threshold VIN > 1.8 V or VOUT > 2.2 V 0.4 V
VMODE_H MODE Logic high threshold VIN > 1.8 V or VOUT > 2.2 V 1.2 V
VMODE_L MODE Logic Low threshold VIN > 1.8 V or VOUT > 2.2 V 0.4 V
RDOWN EN pins internal pull-down resistor 10 MΩ
RDOWN MODE pins internal pull-down resistor 1 MΩ
POWER GOOD
PGDOV PGOOD upper threshold % of VOUT setting 105 107 110 %
PGDUV PGOOD lower threshold % of VOUT setting 91 93 95 %
PGDHYST PGOOD upper threshold (rising&falling) % of VOUT setting 2.5 %
tPGDFLT(rise) Delay time to PGOOD high signal 1.3 ms
tPGDFLT(fall) Glitch filter time of PGOOD 33 µs
PROTECTION
TSD Thermal shutdown threshold TJ rising 170 °C
TSD Thermal shutdown threshold TJ falling 155 °C
TSD_HYS Thermal shutdown hysteresis TJ falling below TSD 15 °C